Hawaslsh
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Hello all,
Apologies for the DaveCAD, hope its still legible. We made a GaN MMIC pictured in the top left. A PA with couplers on the input and output to sample the power. The power is detected by a diode detector that outputs a negative voltage. The GaN PA's gate varies from (pinch off) -2V to (fully on) 0V. The goal of the project is stabilize the gain of the PA over a wide bandwidth (BW). The "plot" on the top right shows the nominal gain of the PA in black. The gain varies from ~16 to 12 dB over the full BW. However, by varying the gate bias appropraty, its possible to achive a stable gain over the full BW (the trace is red). We designed some control circity that adjusts the PA's gate votlage as a function of the two diode dector values.
Above is a simplified schematic of the control circuitry. The two inputs on the left of the schematic are the detected voltages from the input (VDETin) and output (VDETout) of the MMIC. (In the green box) VDETin is scaled by 10dB (10x (V/ V)since we are using square law detectors) to attempt to limit the PAs gain to 10dB as well. The scaled VDETin is fed into another op-amp whose other input is VDETout. Vcont (~middleish node in the scheamtic) presumibly could contol the GaN gate, but its potential voltage swing is too large and will damage the PA.
To that end, Vcont is used to control the gate of a PMOS FET in order to limit the voltage swing between 0V and Vlimit set by a POT and a unity gain buffer. I tried two different FETS, a logic level and non logic level MOSFET thinking that was limit my tuning range, but same results either way.
The over all circuit has a very limited tuning range before Vcont saturates to the negative rail, and my +5V supply (supplying everything) goes into current compliance (its limited to avoid killing the GaN amp). The part I can't figure out, despite my +5V rail going to compliance, its not the GaN PA drawing the current, because the PA doesn't produce gain anymore, perhaps implying the op-amp producing Vcont is oscillating?
I would be nice to simulate the performance of a circuit like this, but I dont really know what parameters would be important to look at / capture to understand stability. If anyone has any advice as to where the circuit could be improved or changed that would be much appreciated.
Thanks in advance
Apologies for the DaveCAD, hope its still legible. We made a GaN MMIC pictured in the top left. A PA with couplers on the input and output to sample the power. The power is detected by a diode detector that outputs a negative voltage. The GaN PA's gate varies from (pinch off) -2V to (fully on) 0V. The goal of the project is stabilize the gain of the PA over a wide bandwidth (BW). The "plot" on the top right shows the nominal gain of the PA in black. The gain varies from ~16 to 12 dB over the full BW. However, by varying the gate bias appropraty, its possible to achive a stable gain over the full BW (the trace is red). We designed some control circity that adjusts the PA's gate votlage as a function of the two diode dector values.
Above is a simplified schematic of the control circuitry. The two inputs on the left of the schematic are the detected voltages from the input (VDETin) and output (VDETout) of the MMIC. (In the green box) VDETin is scaled by 10dB (10x (V/ V)since we are using square law detectors) to attempt to limit the PAs gain to 10dB as well. The scaled VDETin is fed into another op-amp whose other input is VDETout. Vcont (~middleish node in the scheamtic) presumibly could contol the GaN gate, but its potential voltage swing is too large and will damage the PA.
To that end, Vcont is used to control the gate of a PMOS FET in order to limit the voltage swing between 0V and Vlimit set by a POT and a unity gain buffer. I tried two different FETS, a logic level and non logic level MOSFET thinking that was limit my tuning range, but same results either way.
The over all circuit has a very limited tuning range before Vcont saturates to the negative rail, and my +5V supply (supplying everything) goes into current compliance (its limited to avoid killing the GaN amp). The part I can't figure out, despite my +5V rail going to compliance, its not the GaN PA drawing the current, because the PA doesn't produce gain anymore, perhaps implying the op-amp producing Vcont is oscillating?
I would be nice to simulate the performance of a circuit like this, but I dont really know what parameters would be important to look at / capture to understand stability. If anyone has any advice as to where the circuit could be improved or changed that would be much appreciated.
Thanks in advance
