Ok, so it seems if I take 32-bits out of the FIFO instead of 64, then have a 5 stage pipeline, I will require 20 DPRAMs in order to store the data. The post-processing will have to sum the locations in those 20 RAMs into one complete histogram. Reasoning for this:
one 32-bit read from the FIFO actually contains 4 samples, Da, Db, Dc and Dd.
Each one of those will go into a 5 stage pipeline and write to one port of a DPRAM, so that is 5 DPRAMs for Da, 5 for Db, 5 for Dc, and 5 for Dd. The DPRAMs would be 256x16. I have thought about adding an offset to each 256 addresses to make all 5 DPRAMs implement into one DPRAM, but that requires using both ports for the RAM. See next paragraph...
In that case, one port is reading while the other is writing, but then I don't have a port free for the post-processing loop which will be reading and adding them all together. Also, how would that account for two samples which are the same. If the value in memory is 1, the read line will read out 1 (read during write yields old contents), while the write line is writing in a 2....so then a 2 will get written again, and I will miss a count.
I'm trying to get the architecture down before I start coding again. If I am missing something please chime in. I would like to not have to use 20 DPRAMs, but I just don't see how to avoid it at this point. Any suggestions to minimize the # of RAM blocks would be appreciated.