Hi ee1,
You have mentioned about 170ps of violation in place-opt stage.
1) First check the violation is existing between valid half cycle path. (leading edge to trailing edge path or vice-versa)
2) If its not an valid half cycle path and its a genuine full cycle path only, try an incremental optimization on already optimized placement database. If this is also not yielding go for some floorplan changes or grouping of critical modules if any needed.
3) If the violation exist between half cycle path you may see this violation. These violation goes off post-cts.
4) The reason given below.
Assume the clock period of 2ns, setup time 150ps, uncertainity 200ps, datapath delay 1 ns
So Required time = 1 - 0.15 - 0.2 = 0.65ns (1 taken as clock period as it is a half cycle path)
Arrival Time (Datapath Delay = 1 ns
So Slack = -0.35 ns = 350ps.
During placement clock path is ideal and no delay is considered. When you do CTS, because of buffer addition, Latency will add to the clock path (Required time) and this violation will get fixed easily.
Regards,
Rajesh Srinivasa Rao