[consult] power management IC (ON/OFF) detection circuit

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trashbox

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Hi all,

I need to design a circuit in power management IC to detect power key action: in power off state, when detect >50ms High pulse on power key, PMIC should enable system. (in this case, 1Hz clock is always available)

My question is: if no signal from host device (CPU) can be used, how to make it possible that the PMIC is still ON even when users release power key after 50ms? Thanks in advance.
 

use 555 timer

Added after 1 minutes:

on shot multivibrator

Added after 4 minutes:

See the 555 timer chapter of Operational Amplifiers and Linear Integrated Circuits by ~ Robert F. Coughlin (Author), Frederick F. Driscoll (Author)
 

Hi rongo024,
Thanks for your reply. 555 timer just generate a wider pulse from a pulse-trigger. My problem is that I need to detect a 50ms pulse. The attachment is a logic diagram. Thanks.
 

trashbox said:
... how to make it possible that the PMIC is still ON even when users release power key after 50ms?
Click to expand...
May be I don't understand your pb. correctly. Why can't you simply set an RS-FF ?
 

This is a very normal power on requirement. When the key voltage exceeds a certain threshold you start a 50ms timer (I assume the 1Hz was a typo). The output of this timer sets a FF.
 

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