constructing linear saturation states of PMOS netlist

Status
Not open for further replies.
Sort by date Sort by votes
Your "V1 list 0" should in fact be a list of gate voltages
that are 0 (cutoff), slightly below VT but on the slope
(subthreshold), well above VT (linear).

You might find it easier in total, to place multiple devices
with multiple Vgs, Vds forcing sources so you can plot
any / all from a single run. The schematic appears to be
LTSpice, you already have the models (one hopes) and
should be pretty simple to set up (if there isn't already a
LTSpice schematic (.asm?) in the bundle).
 

Upvote 0 Downvote
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…