Jennis
Junior Member level 2
![Junior Member level 2](/styles/images/ranks/clevel2.gif)
Can you please share how do you decide the constraints for input and output ports. Usually it is 20-30% of clock periords but do we really require these constraints if you are doing the synthesis at the chip-level not in block level.
It is also depend on the application but if the design arcehitecture does not have those information then how would designer set those constraints.
Thanks
It is also depend on the application but if the design arcehitecture does not have those information then how would designer set those constraints.
Thanks