constraint randomization in system verilog

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rkini

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I have a task defined within a class as follows:

class test;
....
....

task read_write();

reg [7:0] address;
reg [15:0] data;
....
....
...
endtask

endclass

I want to randomize the address within a certain constraint say from B0 to FF, how do I do that???
 

I have seen examples of randomizing with a specific probability in a class. Can I do the same for an interface signal within the task in my class. What I mean to say is I have the same task within the same class:

class test;
....
....

task read_write();

reg [7:0] address;
reg [15:0] data;
btest_intf.reset = 1'b0;
....
....
...
endtask

endclass

Can I randomize this reset signal with a probability of 20% 1 and 80% 0??
 

Rather than generate random values for each individual field, a better approach is to create a transaction class with random variables and randomize the transaction as a whole. The you can assign the values in your class to the interface signals.

Now you are starting to get into the realm of an object-oriented testbench. And there can be many different ways of doing this. That's why we have methodologies like the UVM to help narrow down your choices.

If you are not quite ready to take on the UVM here is a simple transaction class with constraints.

Code: 
class transaction;

  rand bit  [7:0] address;
  rand bit  [15:0] data;
  rand bit reset;

  constraint a_range { address inside {['hB0:'hFF]}; }
  constraint a_reset { reset dist { 1 := 20, 0 :0 80 }; }

endclass
You have not given us enough details about what you are trying to do, I do not know if this will help you.
 
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    rkini

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Thank you, I will try the transaction class.

Initially I wanted to read and write random values into a set of registers and sweep over a range of addresses. But now I want to randomly generate resets as well as random read- write combinations. I guess I will have to read about coverpoint to make sure the test covers all possible combinations.
 

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