In my design, we have multiple clocks with different frequency, but the clocks have the same source.
(For example, clock A and clock B both are divided from clock S, and Frequency(A) = n*Frequency(B), n is an integer)
There are some logic between the two clock domains, how can I constraint the logic from clock A to clock B, and the logic from clock B to clock A?
If you can confirm that the clkA and clkB ablosutely come from the same source, and according to the design requirement you do want to check the timing between these domain, you can set these clocks in the same clock group. Then tools will check timing in these domains.