Constraint diagram for synthsis

[aomeen]

Hello all,

I'm new in digital design for synthsis. My Manager asked me for a clock constraint diagram and input/output delay constraint diagram for my design.

For the delay constraint diagram, I read in some ASIC book that it's related to time required for the input to be available after the clock edge, and for the output to be available before next edge... The problem is that all my design blocks are ideal so far "No synthsis- No delay !!", so how would I evaluate the constraint delay ?

:?: should I specify it in terms of symbolic blocks delay... i.e assume D-FF has delay δ and Adder has delay Ta ans so on

:?: What about Clock constrain diagram ?

Thanks in advance...

 

[Dr_MS]

Hi,

You should define input/output delays to constraint your design for synthesis.
Imagine that the inputs for your design come from another block and they are not static, you must define an input delay because these inputs will not be immediately available (they have a delay). The clock edge reference gives you the worse case for the delay. The same for the outputs.

 

[aomeen]

Hi,

You should define input/output delays to constraint your design for synthesis.
Imagine that the inputs for your design come from another block and they are not static, you must define an input delay because these inputs will not be immediately available (they have a delay). The clock edge reference gives you the worse case for the delay. The same for the outputs.

You are right, but in order to get how much delay I can tolerate, I must know the delay of the internal blocks of my design, which-as I said- are defined only after synthsis.

Should I define the constraints in terms of these delays ?

 

[yln2k2]

Hi ,


Rule of Thumb for all ports ( except clk) is 40:60 ie

In case if I/P delay you take 40 % clk period and give 60% of clk to out side .

similarly o/p delay take 40% and give 60% to out side .

These % depends on type of design and it will different if your module is talking to outside world ( if you have ports taking to another chip) ...

Regarding clk ingenral you need to take a source latency ( which should come from top level synthesis ) . it is completly depends on your ASIC synthesis strategy ...

feel free to ask if you have any specific doubts .


Thanks & Regards
yln