casey480
Junior Member level 1
I am using a register in a non-typical fashion. The rising edge of signal 'A' will set this register. It is reset asynchronously by signal 'B'.
Signal 'A' is acting like a clock on this register, but not on other logic, so i am hesitant to create a clock on that port. How do i constrain this register properly?
Thanks.
Signal 'A' is acting like a clock on this register, but not on other logic, so i am hesitant to create a clock on that port. How do i constrain this register properly?
Thanks.