Constraining a combo path (Synopsys DC)

[dirac16]

I want to use set_max_delay -from [from_list] -to [to_list] after synthesis to constrain a combinational path having a large delay. This command by itself doesn't do anything useful and in the dc shell it must be followed by other commands for the design to take effect. So if you want to see the effect what next commands do you run in dc shell?

 

[FvM]

E.g.:
compile
report_timing

 

[rca]

right this command does nothing as it is just applying a constraint.
The constraint will be respected by tool mentionned by FvM (compile, synthesis...)
The constraint will be used as a threshold while using a "report_timing" for example.

 

[dpaul]

I want to use set_max_delay -from [from_list] -to [to_list] after synthesis to constrain a combinational path having a large delay.

In the correct design flow procedure, you first complete the constraints file and then proceed to synthesis.
Of course improving the constraints file and running simulation in many designs can be an iterative process.

 

[dpaul]

running simulation in many designs

of course I meant "synthesis"