neocool
Member level 4
I had a question regarding consequitive execution of VHDL statements inside of the process:
here is the code:
Does it delay the clock by 3 cycles or does it execute the code line by line to make BIT_CLK_IN_D3 == BIT_CLK0 after the first run of the process?
How many clocks are needed to make D3 clock == BIT_CLK0? please explain the values of variables for each clock/run of the process.
Thanks
here is the code:
Code:
RECLOCK_000: process(ASYNC_RESET, CLK)
begin
if(ASYNC_RESET = '1') then
BIT_CLK_IN_D <= '0';
BIT_CLK_IN_D2 <= '0';
BIT_CLK_IN_D3 <= '0';
elsif rising_edge(CLK) then
BIT_CLK_IN_D <= BIT_CLK0; --line 1
BIT_CLK_IN_D2 <= BIT_CLK_IN_D; --line 2
BIT_CLK_IN_D3 <= BIT_CLK_IN_D2; --line 3
end if;
end process;Does it delay the clock by 3 cycles or does it execute the code line by line to make BIT_CLK_IN_D3 == BIT_CLK0 after the first run of the process?
How many clocks are needed to make D3 clock == BIT_CLK0? please explain the values of variables for each clock/run of the process.
Thanks