Connecting to an unpacked array in System verilog

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lostinxlation

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Could someone tell me how to connect unpack arrays in system verilog in the following example ?

Code: 
module sub (
input  [31:0] in [0:3];
....
);
endmodule


module top (
input [31:0]  in [0:1];
....
);

sub sub (.in(????????));

endmodule

Now I want to connect primary input, in[0], to in[0] and in[1] of sub, and connect primary input, in[1], to in[2] and in[3] of sub.
I want to connect them like(I know it is not legal, but just gives you some idea on what I want to do),

Code: 
sub sub(.in({2{in[1]}}, {2{in[0]}});


how can I achieve this without assigning in[1:0] to other variables ?

many thanks,
 
Last edited by a moderator:

just as you would access any multi-dimensional array...

input [31:0] in [0:3];

would be accessed like this:

in[unpacked_0_thru_3][packed_bit(s)_31_to_0]

I'll leave it up to you how you want them interconnected (couldn't quite interpret how you wanted to do it)

Regards
 
Last edited:

ads-ee said:
I'll leave it up to you how you want them interconnected (couldn't quite interpret how you wanted to do it)

Regards
Click to expand...
I'm trying to connect the primary inptus to input ports of sub as
in[1][31:0] ---> sub.in[0][31:0]
in[1][31:0] ---> sub.in[1][31:0]
in[0][31:0] ---> sub.in[2][31:0]
in[0][31:0] ---> sub.in[3][31:0]


I don't think the tool accepts
Code: 
sub sub (.in({in[1][31:0], in[1][31:0], in[0][31:0], in[0][31:0]}));
as you mentioned.
 

Oh, wait now I see what your problem is.

You want to connect the following:

sub
in_sub[1][31:0] connects to in_top[0][31:0]
in_sub[0][31:0] connects to in_top[0][31:0]

in_sub[3][31:0] connects to in_top[1][31:0]
in_sub[2][31:0] connects to in_top[1][31:0]

Have you tried: .in(in_top[0],in_top[0],in_top[1],in_top[1])?
 

yes, I have tried it and it didn't work.
I also tried,
Code: 
.in({in({in_top[1], in_top[1], in_top[0], in_top[0]});  // with { and }
but no luck.
 

okay this works:

Code Verilog - [expand]
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`timescale 1ns/1ns
 
module sub (
  input [31:0] in_sub [0:3],
  output [31:0] out_sub
);
 
  assign out_sub = in_sub[0] + in_sub[1] + in_sub[2] + in_sub[3];
 
endmodule
 
module test4;
  reg [31:0] in_top [0:1];
 
  wire [31:0] out_sub;
 
  initial begin
    in_top[0] = 0;
    in_top[1] = 0;
    #100;
    in_top[0] = 32'h12345678;
    in_top[1] = 32'hdeadbeef;
    #100;
  end
 
  sub sub_i (.in_sub({in_top[0],in_top[0],in_top[1],in_top[1]}), .out_sub(out_sub));
 
endmodule
 

I actually find it interesting that this worked. Xilinx's simulators haven't been know to be very good at supporting SV. Even now they don't seem to admit they support it, even though you can enable the -sv switch on command lines and it "accepts" SV syntax.

- - - Updated - - -

lostinxlation said:
Thanks,
Can we not use {2{in_top[0]}} instead of {in_top[0], in_top[0]} ?
Click to expand...

apparently not:
ERROR: [VRFC 10-1329] replication is not allowed in unpacked array concatenation [test4.v:26]

Of course YMMV with Modelsim/Incisive/VCS.
 
many thanks

i tried to connect a replicated pack array(in {2{pack_array}} manner) to an unpack array port, and also tried to connect a replicated single bit wire as in {2{single_bit_wire}} manner to an unpack array port. Neither worked.

So, is it the conclusion that any replication of signals connected to an unpack array port is not allowed ?
 

Well replication results in a packed array so yeah I would think it's not allowed.
 

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