Connecting pads and circuits when doing IC layout

[goatmxj666]

Hello IC experts. I am doing an IC layout in 180nm process. I have a question when placing the PAD.

The PADs I have are stacked from metal1 to metal6 (TOP metal) with all metal vias.

Is it okay to connect CLK signals or analog signals (tens of MHz) to these PADs? Most of the signals are connected through buffers and I think it will be fine (I can drive down to 10pF), but I am worried about the output signals that are not connected to buffers.

Is it okay to connect these unbuffered output signals to the PAD now or is it better to connect them to a PAD consisting of only the top metal (M6) and PAD layer?

Any answers would be greatly appreciated.

 

[goatmxj666]

Hi IC layout experts. I am doing a layout in 180nm process.

I have a question when connecting the PAD and the circuit.

When the PAD size is 70umx70um and the thickness of the metal to be connected to the node is 0.5um,

Is it better to connect the metal thicker (ex. 50um) from the PAD and reduce it to 0.5um metal thickness after reaching near the circuit, or is it better to connect it all the way to the PAD at 0.5um? If not that, do you recommend connecting it with a medium thickness metal like 10um?

If you have any tips on connecting to the pad, I would really appreciate it.

 

[dick_freebird]

Pad cells often include ESD clamp features which would be key to any core signal exposed to outside.

While I have often brought signals out bare, for low level char / test, this always demands very careful handling and test forcing, and results in a lot of damage anyhow (along with the fun of checking every data set for signs it came from a compromised unit).

Your call, but I advise buffering anything that can be so, and deliver "whatever". Put a buffer with free (protected) input & output to de-embed its contributions.

 

[sidun.av]

Hi @goatmxj666 ,
1. There is no need of a thicker metal for a subcircuit-to-pad routing, unless IR drop is a concern. Otherwise, a wide metal will give you more capacitive parasitics that might affect signal integrity.
2. As mentioned previously, buffering signals before bringing them out of chip is always a good idea. Moreover, placing a secondary protection might be a good solution for some sensitive signals.
3. It's better to connect CLK and analog signals through dedicated analog pads, they usually have low capacitance which makes them easy to drive and they do not corrupt the clock signal.
Hopefully, that helps.

 

[goatmxj666]

Pad cells often include ESD clamp features which would be key to any core signal exposed to outside.

While I have often brought signals out bare, for low level char / test, this always demands very careful handling and test forcing, and results in a lot of damage anyhow (along with the fun of checking every data set for signs it came from a compromised unit).

Your call, but I advise buffering anything that can be so, and deliver "whatever". Put a buffer with free (protected) input & output to de-embed its contributions.

Thank you for your response! I will take note.

--- Updated Tuesday at 5:28 AM ---

Hi @goatmxj666 ,
1. There is no need of a thicker metal for a subcircuit-to-pad routing, unless IR drop is a concern. Otherwise, a wide metal will give you more capacitive parasitics that might affect signal integrity.
2. As mentioned previously, buffering signals before bringing them out of chip is always a good idea. Moreover, placing a secondary protection might be a good solution for some sensitive signals.
3. It's better to connect CLK and analog signals through dedicated analog pads, they usually have low capacitance which makes them easy to drive and they do not corrupt the clock signal.
Hopefully, that helps.

Thank you for this very helpful answer, it made me aware of things I didn't know.