Connecting FPGA's LVDS trasmiter to ethernet cable

[Joana]

Hi
I'm connecting cyclone 2 lvds transmiter to 3 meters long ethernet cables(RJ45 connector), besides impedance matiching, sould i consider any other issue for this conections?

Thanks
Joana

 

[dick_freebird]

I suppose you ought to consider whether you'd prefer
source, shunt or AC-coupled termination, but CAT5 is a decent
LVDS wire (at least, at modest data rates).

But 3 meters is about 10nS time-of-flight, and at over 50MBPS
(even nicely terminated) you may see some interesting
intersymbol effects. You might want to begin at lesser
line length, verify things work at 10cm before trying to slap
that long line around.

 

[FvM]

See a 240 MBPS waveform driven from a Cyclone III LVDS driver (with E_3R I/O standard). In this case, DC balanced 8b/10b encoding is used to allow clock recovery and and transmission over ethernet magnetics. The cable length has been 3 or 5 meters in this test.

 

[Joana]

Thanks all
I found an intersting articale about this issue
https://focus.ti.com/lit/an/slyt163/slyt163.pdf