Connect SystemVerilog interface to Verilog module ?

[davyzhu]

Hi,

I want to write SystemVerilog testbench for traditional Verilog module.
But I have no idea how to SystemVerilog interface to traditional Verilog module? Can I both use modport and instance the module? Or is there any walk around method? Thanks!

//----- Verilog Module-----
module dut(
    CLK,
    RESET,
    DATA,
    ... ...
);
input CLK, RESET;
output DATA;
...
//-----------------------------------

and

//----- SystemVerilog Interface-----
interface dut_tb_if;
bit clk,reset,data;

modport... ...
//---------------------------------------------

Best regards,
Davy

 

[maxsnail]

is this a way?
dut_tb_if dut_if;
wire clk = dut_if.clk;
connect clk to module.

 

[spauls]

Please see system verilog LRM !!
Else search in www.verificationguild.com

 

[elec_student]

Hi Yes u need to declare an interface and modports to indicate direction. I am uploading one ppt. Kindly go through that. I think that will be beneficial for you.

 

[darylz]

is you use vcs, pls check the guide in it