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Connect SystemVerilog interface to Verilog module ?

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davyzhu

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Hi,

I want to write SystemVerilog testbench for traditional Verilog module.
But I have no idea how to SystemVerilog interface to traditional Verilog module? Can I both use modport and instance the module? Or is there any walk around method? Thanks!

Code:
//----- Verilog Module-----
module dut(
    CLK,
    RESET,
    DATA,
    ... ...
);
input CLK, RESET;
output DATA;
...
//-----------------------------------
and
Code:
//----- SystemVerilog Interface-----
interface dut_tb_if;
bit clk,reset,data;

modport... ...
//---------------------------------------------
Best regards,
Davy
 

is this a way?
dut_tb_if dut_if;
wire clk = dut_if.clk;
connect clk to module.
 

Hi Yes u need to declare an interface and modports to indicate direction. I am uploading one ppt. Kindly go through that. I think that will be beneficial for you.
 

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
is you use vcs, pls check the guide in it
 

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