congestion at the centre of the core

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jitendravlsi

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Hi All,

relative to floorplan stage

Please tell me all the possible reasons why the congestion takes place at the centre of the core?

or in other words

Suppose you have a square core and facing congestion only at the centre of the core. Then what may be the reasons for this?

what are the ways to solve this congestion?

THANX
JIT
 

check for the cell density in the place where you are seeing the congestion.
Also, keep an eye on the cell types present in that particular location.(For eg:: having AOI or some complex cells having high pin density might cause congestion issues)
If any of them has pin access problems they also might cause congestion, check that issue as well.
 


Dear

your may be one of the reason to face congestion. but why the more number of complex cells will give congestion in centre of the core?

This may give congestion anywhere in the core( any corner of the core or along the boundary of the core.

what may be the reason if we face congestion only at the centre of the core?

I hope you got my question now.......

by the way thanks for reply.......... a nice try..............
 

I had just given the various reasons for congestion.

Suppose,If you are having bist controller logic and it communicates with all the logic in the chip.So, if the logics which are present in all the four corners are trying to pull the logic then placer might have achieved better global soln by placing the bist logic at the center, which might be the cause for the ur congestion.

Check the cell density setting you are providing to the tool.If possible provide the max cell density setting as 0.8 or spread the cells where you are seeing high cell densities.

Supporting my earlier statement, if you are having more complex cells like AOI or OAOI which will have more number of pins.If the router will not be able to find enough resources it can lead to congestion.Always it is preferable not to use complex cells in the congested designs.
 

    jitendravlsi

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suggest me how to remove this congestion?

Added after 1 minutes:

is there any other reason for this type of congestion?
 
give me atleast three reasons for this.
 

 

    jitendravlsi

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Thanks Nashim,

Please tell me something about Cell Padding:
1) when we do cell padding
2) where we do cell padding
3) how we do cell padding
4) What the cell padding does?
 

Hi,
I hope the following might be the reasons for the congestion at the centre:
1) core has macros on the edges
2) only centre is left for the std cells
3) std cells have lot of interaction
4) the macros are also not rotated properly based on IO pin placement
5) the placement blockages are not put properly
6) there are lot of cross fly lines

Please let me know if i am wrong.
Please add ur points too.

Thanks,
Sowmya.
 

    jitendravlsi

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check for your macro & I/O placement, which will decide the std cell placement, check for any zig zag routing happening,, are there any modules got splitted.
To avoid congestion
>check the placement of standard cells first, is the placement of the module as expected or not.
>I agree tat cells with many pins will cause routing congestion, i had seen in my recent implementation NANDS with 4 inputs were causing congestion as thy are being used in data path and placed very near by. avoid these type of cells,
>you can use density screens
>check for whether horizental/vertical congestion and if possible change the aspect ratio accordingly to meet the demand of the tracks.
 

1. check Macro placement, if your macro placement is not well, maybe the routing resource will be eat.
2. check the placement & Routing option. To read the help page of the routing & plcement option and then try some options on / off, you can get different result ....
3. check the timing setup.
 

std cell pading is used to "reserved" place for futur used, but the std padding can be apply for a sub-hierarchy design. the futur used could be to fix the setup by adding strong buffer, if this congested area contains mainly FF, to reserve place for the clock tree buffer....

you could also limited the std cell utilization by soft placement blockage (60% of usable for example), this solution is more physical oriented, you can specify the complete row area or a sub-part. In case to define a sub-part, the placer can choose to move out this region the congested point and you have always the congested point but not any more in the center .
 

    jitendravlsi

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