congestion at low utilisation region

[biju4u90]

In my design, suppose I have local congestion in an area where the standard cell utilisation is very low, say only 30%. What could be the reason for it and how can I solve it?

 

[ThisIsNotSam]

In my design, suppose I have local congestion in an area where the standard cell utilisation is very low, say only 30%. What could be the reason for it and how can I solve it?

some cells are naturally hard to route. I have had designs where I had to remove every xor3 cell, for instance.

 

[Prashanthanilm]

There might be High Density Cells like XOR3/MUX where the No of Pins are close to Number of Placement grid.

If these case, check the Metal access points for these Pins.
Your Pin should have at-least 2 Metal Hit Points for the router to connect.

 

[biju4u90]

There might be High Density Cells like XOR3/MUX where the No of Pins are close to Number of Placement grid.

If these case, check the Metal access points for these Pins.
Your Pin should have at-least 2 Metal Hit Points for the router to connect.

How can I deal with the issue in such a situation??

 

[Prashanthanilm]

Check the Cell Level Pin Placement.
1. Whether the Pins in the Cell Level have options for the router to route.
Eg: Output Pin Y, should have at-least 2 or more access point meaning where the Router can place the Via and make the connection)
This should be taken care

2. If the above is not possible, place a FILL cell beside high density cell to borrow a space for the corner pins
Check on EDA site for more information on this.

But for 30% Utilization, You need to take care in Layout Level. Have a look at Cell Level Layout on the Pins where the router is congested.

 

[ThisIsNotSam]

Check the Cell Level Pin Placement.
1. Whether the Pins in the Cell Level have options for the router to route.
Eg: Output Pin Y, should have at-least 2 or more access point meaning where the Router can place the Via and make the connection)
This should be taken care

2. If the above is not possible, place a FILL cell beside high density cell to borrow a space for the corner pins
Check on EDA site for more information on this.

But for 30% Utilization, You need to take care in Layout Level. Have a look at Cell Level Layout on the Pins where the router is congested.

What you are suggesting only works if modifying the cells was a real possibility. it isn't. no one is going to modify 3rd party IP, for several good reasons.

Just stop using the problematic cell. At synthesis level, just set a dont_use constraint. At physical level you can do an ECO-like replacement.