Indrajit Ghosh
Junior Member level 2
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i have written a verilog code , and a part of the code looks like this....
now what i want to do is that i want to disable the 'rst' signal whenever the if statement i.e " if(rst) " is executed,the rst signal is a net type....where to put the disabling statement?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 always @(*) begin if (cs)begin if (rst) begin u_last=u_initial; end else begin ce1=1'b1; ce2=1'b1; ce3=1'b1; u_last=u_temp; end ce1=1'b1; ce2=1'b1; ce3=1'b1; ui_new=u_temp; end else begin ce1=1'b0; ce2=1'b0; ce3=1'b0; u_last=u_temp; ui_new=u_last; end end
now what i want to do is that i want to disable the 'rst' signal whenever the if statement i.e " if(rst) " is executed,the rst signal is a net type....where to put the disabling statement?
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