confusion about generated clock when specify cts

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Kaisia

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when i specify cts information in encounter.
i get some information just like:

Input pin top_inst/clk_ctrl_inst/div_reg/CP (stdcell SDFF) doesnt have timing arc to go out.

what is the exact meaning?

ps:this reg is used to generate a divided clock, and it has been specified as a generated clock. additionally, this clock doesnt has any sink in my top module. it would go out to get used in other place.
 

If i understood correctly you are trying to build the CTS from pll_clk and this clk goes to divider (flops) and output of those divider will act as clock .
Then
1.why r u building the CTS from root pin to this divider flop if there is no other sink to the root clock except divider flop.
If there are other sinks to the root clk then you can specify divider flop CK pin as leafpin in your CTS spec file.
2. might be you can specify this divider flop as through point ----not a good idea
 


it's already recognized as a through pin by tools (because it's defined as a generated clock).
my confusion is why report it no timing arc from the very reg input pin CK. the divided clock will apply for another place which no in my top.
 

r u specifying the root clk as AutoCTSRootPin ?
As far i know tools will not treat flop as through point by default ...
 

srihari_adem said:
r u specifying the root clk as AutoCTSRootPin ?
As far i know tools will not treat flop as through point by default ...
Click to expand...

when that point( the dff output Q) is defined as a generated clock, the backend tool will recogize it and treat it as a through pin.
 

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