Confusion about DAC's sampling rate

[ilovephysics]

I am an extreme noob when it comes to DAC. I am looking at AD9780 right now. I want to use a DAC to produce the smooth rising edge and falling edge of a square pulse. I am controlling the width of the square pulse on the order of nano seconds so preferably edge time also should be on the order of ns. Therefore I need a fast DAC. By the way, I am controlling the DAC with an FPGA.

here is the data sheet from Analog Devices,

(Sorry can't post link on my first post, I will add it later once it's posted)

First of all, does this DAC support serial data in? I thought so for quite a while but not sure anymore. It does support SPI. Does that mean I can send my input data serially in through this port. Or this port is for configuring the DAC only and not for actual data writing.

Another thing that really confuses is that it says that this DAC has a sample rates of up to 500 MSPS. But it also says that the maximum frequency for the SCLK (for SPI) is only 40 MHZ and all data are written in on the rising edge of SCLK and outputted on the falling edge of this clock. If this is so, how can we get the 500 MSPS? I have a sinking suspicion that you can get 500 MSPS only by using the LVDS parallel input interface. Am I right?

Thanks a lot for your help!

---------- Post added at 06:01 ---------- Previous post was at 06:00 ----------

here is the data sheet for the DAC

AD9780 | Dual 12-Bit, LVDS Interface 500 MSPS DAC | All D/A Converters | Digital to Analog Converters | Analog Devices

 

[zakipour]

DACs are not good devices to control the pulse width. The best way to produce a square wave with determined width and frequency is using a timer. Using an FPGA you can easily build such a timer.

 

[ilovephysics]

DACs are not good devices to control the pulse width. The best way to produce a square wave with determined width and frequency is using a timer. Using an FPGA you can easily build such a timer.

I am not using the DAC to control the pulse width. My FPGA can already do that. I just want the DAC to do the smooth rising and falling edge since FPGA can only output sharp logic levels.

 

[FvM]

I have a sinking suspicion that you can get 500 MSPS only by using the LVDS parallel input interface. Am I right?

I'm not sure about your level of basic electronic engineering knowledge. But to make a 12 Bit DAC send an analog signal with a speed 500 MS/s, you obviously need to send a stream of parallel 12 Bit data words at 500 MHz rate. Serial transmission is impossible for sampling rates above e.g. 50 MS/s. The SPI interface is for configuration only.

As a special point, the said AD9780 is a dual channel DAC and expects interleaved samples at 1000 MHz data rate with 500 MHz clock (using double data rate). But it should be able to output identical data on both channels if you send 500 MHz with single data rate.

 

[keith1200rs]

I would have thought some analog circuitry to control the slew rate of a square wave would be an easier solution (but then I am an analog designer).

Keith