dhaval4987
Full Member level 3
Dear all,
I am working on a design of a voltage regulator which involves using a diffpair in a closed loop.
However- at low load current the phase margin sucks and the gain is in negative, but to my surprise, it still works in transient analysis. How can this be possible? whats going on?
Any suggestions?
I am working on a design of a voltage regulator which involves using a diffpair in a closed loop.
However- at low load current the phase margin sucks and the gain is in negative, but to my surprise, it still works in transient analysis. How can this be possible? whats going on?
Any suggestions?