confused about PLL peaking

[hearter]

here is what's confusing(assume type 2 charge pump PLL):
The peaking is caused by zero and pole(from the LPF, or some say parasitics), so to reduce the peaking, you want to move zero close to the pole to reduce the peaking, but in simulation I have to increase my cap(in series with R) in the LPF to reduce the peaking. here is the confusing part, increasing cap will move zero to origin, hence further away from the pole.

sth is not right, any one can shed some light on.

appreciate.

 

[LvW]

Hello HEARTER,

when you speak about "peaking" you are in the linear small signal frequency domain, right? (under lock-in condition !)
Don`t forget that your PLL is a strong non-linear device which has to operate under out-of-lock conditions.
With other words: It is correct that by increasing the capacitor the zero is shifted towards the origin- however, the PLL moves from 2nd order to first order! And a first order loop exhibits of course no peaking - but will the PLL work as you like ? I doubt, since there will be practically no loop filter.

Quote: increasing cap will move zero to origin, hence further away from the pole.
By the way: Where do you expect the pole ???

 

[biff44]

Yep, that is what you need to do.

Peaking is the mathematical equivalent of trying to divide by 0. Closed loop transfer function is T(s)=G(S)/(1+GH(s))

So they |GH(S)|=1, and ang(GH(s))=180 degrees, then T(S)=G(S)/(1-1)= =G(S)/0 = unstable. If you are even somewhat close to this, you will get peaking.

In a PLL, the vco has one pole, and your loop filter has another pole, so that is -180 degrees of open loop phase shift right there. If you do nothing more, you are guaranteed an unstable loop. But if you add a zero, you can add +90 degrees of phase shift to the open loop, and make the control loop more stable.

So, you need the zero to occur at a LOWER frequency than the loop filter pole, so that when the open loop gain crosses |GH(s)|=1, you are nowhere near having ang(GH(s))=-180 degrees. A common phrase control engineers say is "you must cross the unity open loop gain with a slope of 20 dB per decade".

Read some good basic control theory book, like Kuo, to learn more.

 

[LvW]

Quote bif44:
So, you need the zero to occur at a LOWER frequency than the loop filter pole


Hi BIF44,
I suppose you simply have produced a typing error by asking for a zero LOWER than the loop filer pole. Just the opposite is true! Otherwise one cannot guarantee the 20-dB-slope at the open loop crossover frequency (as required for stability).
Regards

Added after 4 minutes:

Hi HEARTER,

what amount of "peaking" ?
A second order response without any peaking corresponds to a phase margin of app. 65 deg. Thus, for a lower margin (which very often is acceptable) there must be a certain degree of peaking. Therefore my question.

 

[biff44]

Yeah, now that I think about it, you are right. You have one pole at DC, and another pole in the loop filter, and THEN you have the zero (well enough ahead of where the open loop gain crosses 0 dB). Thanks for the correction.

 

[hearter]

thanks everyone, didn't check for some days.

I totally understand what you saying. I just don't know how to relate the peaking to the zero cap in LPF.

I appreciate the explanation, increasing the zero cap is actually moving toward type I PLL instead of type II. but increasing 10-20% zero cap, you are still dealing with type II, 2 poles in origin, then zero, then pole from LPF.

so question still remains, why increasing zero cap will reduce peaking while i is actually moving zero away from the LPF pole. my understanding is to keep the zero close to pole to reduce peaking. but reality is the opposite. I have been doing PLL for years, know how to handling peaking. but just want to hear from everybody how to explain.

Added after 1 hours 56 minutes:

also can anyone shed some light on charge pump current impact on peaking, hence the spur, how do you relate them and quantify?