confused about PLL design ...

cp-pll loop filter transfer function

while trying to understand THE PLL to design pll freq synthesizer i faced many problems...

sometimes the loop filter is just a low pass filter... they calculate its transfer function then use it to calculate the over all transfer function of the PLL... then they use some parameters to determine the valuse of R and C

sometimes the loop filter is just a compination of shut capacitor and resistor and sometimes a low passfilter after it ! they say its for charged pump pll ?????
the calculate the loop filter impedance and ask you for some paramters to choose the RC values


MY QUESTION HERE :

iwant to design a single frequency PLL... no channel spacing no maximam and minmum freuqency no hop time!.... ihave already PLL chip that has a charge pump...so how can i design such a system ???

how to choose values or r and C ...

thanks in advance

The loop filter configuration depends on thephase detector used...

If the PD is an XOR gate or an analog mixer, the o/p signal of the detector is a voltage signal. So, for this type of PLL the loop filter is an R-C lowpass filter (with filter o/p taken on the Cap).

However, when using a PFD-CP comnibation, the o/p signal is a current signal. To low pass filter this signal (i.e. to obtain a low-pass filtered output voltage), you would simply use a cap in parallel with a resistor. then I*Z is a lowpass filtered o/p voltage resulting from the vharge-pump current.

However, the loop filter used usually with PFD-CP pll's is a series R-C section with the o/p taken on the whole combination. This filter makes the system a Type II, 2nd order system. A major advantage of such a system is that the residual phase error due to an input frequency step is zero (This is not the case with type I, 2nd order systems).

Concerning your design, could yo please clarify what chip you are using and what phase detector it employs?

If you are making a synthesizer, then how do u say that hop-time is irrelevant?

Hope this is useful...

it's MC145152-2
www.freescale.com/files/ rf_if/doc/data_sheet/MC145151-2.pdf

the problem is icant determine if this chip has a charge pump or not ??

and i want to generate only 1 single frequency ? so why hops ?

when using charge pump pll's, rc gives a pole and zero, lowpass just gives pole. you need the zero to counteract the Rout-C pole of the pump, and then your pump/filter combo acts like a true integrator. I'm not sure you can stabilize your loop (without HEAVILY overdaming) without the R-C pair. Trust the zero!

but anyway, let's move on to your chip. this one is a bare-bones, NOT CHARGE PUMPED pll building block. the phi outputs are basically the outputs of the d-flip flops that are used as phase frequency detectors. the PD output goes high or low depending on the phase frequency detect. you can use the PDout pin to essentially implement a CP-PLL but it is not a true CP because it is not pumping constant currents. i like it, i think you should continue to use this chip unless you really NEED charge pumping. for your circuit, i think this chip will suit you just fine.

ps - do you know how phase frequency detectors work? there are a million articles on google if you dont. basically, if referece clock rises and VCO has not yet risen, output goes high to speed up VCO. if VCO rises first while ref clock has not risen, output goes low until ref clock rises. in essence, the edge to edge difference is integrated every cycle until the difference is zero. now your VCO = Refclock.

the pin you want to use is the PDout pin, like the circuit shown in figure 3. This pin goes high if VCO is too slow, goes low if VCO is too fast, and is Hi-Z if you are in lock. Therefore it's perfect for charge pumping. The first resistor (touching pdout) converts the 0 or Vcc signal at PDout to a current. This current is fed to (or pulled from) the RC loop filter.

So let's say your VCO is 5MHZ at 1V. Upon startup, the loop filter is at 0, so the PDOUT pin will be almost always high, bringing the filter up with a current of Vcc-Vfilter/Rout where Rout is the resistor touching the PD pin. As the VCO frequency approaches the reference frequency (assuming any dividers of course) the "high time" of the PDout pin gets thinner and thinner until it is no longer pulling up. If VCO is too fast, PDout will give thin slices of GND to pull down the VCO voltage in a similar manner.

Let me know your progress (post here for all to learn!). This chip may not be a true CPPLL but it's close enough to get all the benefits. You just need to cleverly choose your resistor - good luck!

ok ;
1-so PDout correction pulses are current pulses ? or volatge pulses ?

2-when using PDout do i have to calculate the loop filter transfer function as Vo/Vi or as Vo/Iin = Z(s) ???

3- plus ive seen a design somewhere on the web ..uses a combination of shunt capacitor and resistor at the output of PDout!!!!!!and a series resistor after that ???

I recommend you study first some basic concepts in rc filter. Impedance calculus and bode diagrams.

I am going to try in simple words:

The function of this filter is to eliminate high frequency components and ripple in Vcontrol of the vco, for this reason it has to be a low pass filter: RC serves and a shunt C serves to eliminate ripple. Normally shunt C is not greater than 10 times C of RC. You can put another filter after that to improve your filtering but you need to worry about stability. Now you need to study compensation concepts.

I expect this could be useful for you.

jotamario ..ok iunderstand RC filters....
but

a capacitor wont form a low pass filter alone! it need a resistor !

what im asking for here is....

if the PDout of the PLL is current pulese it will need a shunt capacitor first to convert it to voltage...a second stage after then will require additional LOW pass filter for higher frequency noise...

but as someone said this chip doesnt has a charge pump ..so the output is voltage pulses ? so why whould they use a shunt capacitor with resistor before the low passfilter in the loop filter design

maybe i missunderstand something...that causes all this trouble for me!


thanks in advance

wait - i said it. and it was only two posts ago? hmm.

look at the schematic marked figure 3. this is the filter you will make and feed to your vco. you can connect the rest of your circuit any way you want, but the filter you should use is the filter of fig 3. I believe you will use Vo/Vi..

PDout is a voltage output. on the schematic, the first resistor (touching pdout) converts the voltage pulses to current, then the next R,C pair are the filter.. The voltage at the center of the two resistors is the analog control voltage for the VCO.