Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Conformal lec map issues

Status
Not open for further replies.

skyworld_cy

Junior Member level 3
Junior Member level 3
Joined
Jun 29, 2011
Messages
31
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,288
Activity points
1,513
Hi,
I'm new to conformal lec and confused by some results.

as figure shows a RTL compared to synthesis netlist:
Screenshot 2021-02-13 183730.png


the golden has not-mapped DFF as 21131 while netlist has only 13 DFF not mapped. Does this mean the RTL has so many redundant logic to be optimized by synthesis tool? thanks.
 

What are the not-mappped DLATs are? Are they clock gating? Have you turn on clock gating remodelling? It is abnormal because there are often not much clock gating in RTL.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top