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with the ds1868 picc drivers
after some testing to confirm that the bit b0 never gets set in the picc driver
for the sout b0 stake select bit
i am right
when i run a simple clocked loading b0.. test design
the status window in isis updates with the bo bit setting
notice below the
cmd[0]=pots[0];
cmd[1]=pots[1];
cmd[2]=0; this shurly should reflect the state of pot_num
being 0 or 1 in value
so would read
cmd[2]=pot_num;
can someone advise me if i am correct in this assumption or maybe i need also to shift its value to the msb of that byte with a shift<<7 or something similar
if i am right i have fixed the last issue
{not a problem with the the designs or the dll it runs fine purly in picc}
void set_pot (int pot_num, int new_value) {
BYTE i;
BYTE cmd[3];
BYTE pots[2];
if (pot_num >= NUM_POTS)
return;
pots[pot_num] = new_value;
cmd[0]=pots[0];
cmd[1]=pots[1];
cmd[2]=0; //<<<here
for(i=1;i<=7;i++)
shift_left(cmd,3,0);
output_high(RST1);
delay_us(2);
for(i=1;i<=17;i++) {
output_bit(DI, shift_left(cmd,3,0));
delay_us(2);
output_high(CLK);
delay_us(2);
if(i==17)
output_low(RST1);
output_low(CLK);
delay_us(2);
}
}
after some testing to confirm that the bit b0 never gets set in the picc driver
for the sout b0 stake select bit
i am right
when i run a simple clocked loading b0.. test design
the status window in isis updates with the bo bit setting
notice below the
cmd[0]=pots[0];
cmd[1]=pots[1];
cmd[2]=0; this shurly should reflect the state of pot_num
being 0 or 1 in value
so would read
cmd[2]=pot_num;
can someone advise me if i am correct in this assumption or maybe i need also to shift its value to the msb of that byte with a shift<<7 or something similar
if i am right i have fixed the last issue
{not a problem with the the designs or the dll it runs fine purly in picc}
void set_pot (int pot_num, int new_value) {
BYTE i;
BYTE cmd[3];
BYTE pots[2];
if (pot_num >= NUM_POTS)
return;
pots[pot_num] = new_value;
cmd[0]=pots[0];
cmd[1]=pots[1];
cmd[2]=0; //<<<here
for(i=1;i<=7;i++)
shift_left(cmd,3,0);
output_high(RST1);
delay_us(2);
for(i=1;i<=17;i++) {
output_bit(DI, shift_left(cmd,3,0));
delay_us(2);
output_high(CLK);
delay_us(2);
if(i==17)
output_low(RST1);
output_low(CLK);
delay_us(2);
}
}