configuration pins and its behaviour in spartan 3AN fpga

Thread starter sriharsha.hs
Start date Nov 18, 2013

Status: Not open for further replies.

Nov 18, 2013

sriharsha.hs

Junior Member level 3

I am using spartan 3an for my application. I am using non volatile flash to store my bit stream and using Internal Master SPI Mode. During the configuration stage, some of the dual type I/O's has to be taken care as shown in UG332(217 page). I have connected the mode select pins m[2:0] to 011.

What should be the logic level of PUDC_B, PROG_B, INIT_B (Bidirectional pin) and VS[2:0] before the configuration.

Since I am using Internal Flash, what should be the logic level of vs[2:0] ?

Please let me know.

Anything is appreciated.

Thank you.

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