Conductor Spacing for a micro-controller board

[sabu31]

Dear All,

I am making a custom board for using Texas Instruments TMS320F28027. My main concerns are regarding the trace spacing.

I have PWM signals total 8 numbers (4 channels) with typical use frequencies up to 100kHz. Along with this, there are ADC signals. In various PCB design articles/videos, it's mentioned as a thumb rule to keep the space between traces at least 3 times its track width. My signal traces are 10 mils wide. I want to know if this rule of 3 times width is applicable for 100kHz signals. Also, what should the spacing be between the analog and PWM traces to reduce cross-talk.
All analog and PWM signals are coming to a single 22 pin (2.54 mmm pitch and in 2 rows of 11 pins) connector which will be connected to a main power converter board.

 

[barry]

It’s not the frequency that matters, it’s the rise/fall time of the edges that cause interference. A rule-of-thumb is just that, it’s not an absolute rule. If you REALLY want a definitive answer, you’ll have to do an analysis of your specific layout.

A question like “what should the spacing be between the analog and PWM traces to reduce cross-talk.” is meaningless. ANY spacing will reduce crosstalk, more spacing will reduce it more. How much crosstalk can you tolerate?

 

[sabu31]

Hi Barry,

Thanks For the reply. The typical rise time of pulse is 50ns. As I am from power background, I want to know what is acceptable level of spacing for micro-controller traces (adc (typically dc signal or ac below 60kHz frequency sine) , PWM (around 100khz square wave (say 50ns rise time) etc) . I am newbie to signal integrity concept.

 

[FvM]

In the discussed signal frequency range, you are mainly looking at capacitive coupling. It can be calculated using PCB design tools, distance to ground plane (if any) is an important parameter.
Capacitance value can be entered in SPICE model to check crosstalk effect.

A possible crosstalk cause is having too few ground pins for your plug-in connector.

 

[KlausST]

The typical rise time of pulse is 50ns.

this sounds rather slow.
Where is this value from?

Capacitive crosstalk also depends on impedance (not characteristic impedance) of nodes / traces nearby. Here the analog signals.

In case of analog signals, it´s always a good idea to keep the lengthy part low impedance and put an appropriate low pass filter at the target side.

Also - if possible - use an ADConversion frequency synchronous to the PWM frequency and place the sample_to_hold_edge far from the PWM edge.

Klaus

 

[marce]

Quite often spacing depends on the density of the design...
A common, non BGA analogue/digital design will often have a track with of 0.20mm and a minimum spacing of 0.20mm, obviously where possible you increase the space between traces. On BGA boards, these are often reduced to 0.10/0.10mm Tack/gap and on some boards with really small BGA's 0.075/0.075mm Track/Gap, often with microvias...
I would also start using hard metric for your designs, the majority do these days as most devices are hard metric. This is an informative link:

https://www.ipc.org/system/files/technical_resource/E18%26S12-4.pdf

For the device chosen, I would use 0.20/0.20mm track gap, with 0.60mm via land with a 0.30mm finished via hole. These Sizes are standard (and have been for many years, I have used them since the late 1990's) and will cause no manufacturing issues.

 

[FvM]

0.15/0.15 mm is also supported by all manufacturers without extra costs.