Conditional statement in SV for loop

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surisingh

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Hi,
I need to implement one logic in System verilog. Here is the snippet of code:

for(int i=0; i<max_count; i++) begin
if(aid_queue == bid_queue[bid_count] && queue_index != i) begin
queue_index = i;
end

Here initially queue_index is high value, say 32'hFFFFFFFF, I need to search the entire aid_queue for the particular value.
once the value is found, i am setting the queue index to that index, say the matching index is 5.

When next time this loop encountered, I need to search the entire aid_queue EXCEPT the queue index 5. Now if the
value matches and the queue index is 7, next time i have to search the entire queue EXCEPT the queue index 5 AND 7 and so on...

How can I do that in SV using just for and if loop.

Thanks
Suri
 

Obviously, the used indices have to be remembered in a bit array.

The real problem is beyond the simple behavioral coding question. Although you can describe the intended behaviour in HDL, e.g. System Verilog, it may be effectively impossible to synthesize it in parallel logic with reasonable effort.
 

Thank you, Can you please explain with the snippet of code?

Thanks
Suri
 

Can you explain why you have the requirement to implement with just a for and if loop? Does your code need to be synthesizable? Are you allowed to add more registers? When you say "the next time the loop is encountered" what kind of loop is this loop nested in?
 

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