[SOLVED] Conditional operator & case

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fragnen

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Can below conditional operator be used inside sequential always block?
c ? a: b;

Can case statements be used inside sequential always blocks?
 

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Yes on case inside always -



Regards, Dana.
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fragnen said:
Can below conditional operator be used inside sequential always block?
c ? a: b;

Can case statements be used inside sequential always blocks?
Click to expand...

Try a test case on the operator question.....

Regards, Dana.
 
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danadakk

Your link is showing case statement inside combinational always block. The post#1 was for case statement inside sequential always block. Also looking for use of conditional operator pr case statement inside sequential always bloc for synthesizable codes.
 

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Why don't you simply review the Verilog language reference manual or a text book. You'll see that there are no restrictions regarding usage of case statement and conditional operator.

According to Verilog nomenclature, all always blocks, also combinational always(*) blocks are considered sequential blocks.
 
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The always construct is an instance of a procedural context. Procedural code may contain compound statements enclosed in an begin/end block, in which case those statements execute sequentially. This is in contrast to a fork/join block which execute those statements concurrently. Whether that always construct contains a singe statement or compound statements executing sequentially is independent of the construct representing sequential or combinational hardware.

You typically see the conditional operator ?: used outside of a procedural context, line a continuous assign statement in place of a the procedural if/else statement, but there nothing preventing you from using it wherever an expression is allowed.
 
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FvM/Dave_59

By sequential always block those always blocks which is triggered on either posedge or negedge of a variable like clock or reset, are being referred in the query at post#1. Can you please now reply to the queries at post#1? Can you please also state whether such a conditional operator or case statement inside an always block which is triggered either by posedge or negedge of a variable like clock or reset, are synthesizable or not?

Regards
 

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If you understand how an always block works, you won't ask. The assignments in the case statement or an assignment with conditional operator behave just the same as simple assignments, which are "triggered" by the respective clock or - in hardware view - infer a register. Case or conditional operator creates different combinational logic in front of the register.
 

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Will there be cons if a flipflop is coded as rtl in the following way instead of using traditional if-else inside the same always block ?

always @(posedge clock or negedge rst)
(!rst) ? (q<=0): (q<=d);
 

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fragnen said:
Will there be cons if a flipflop is coded as rtl in the following way instead of using traditional if-else inside the same always block ?

always @(posedge clock or negedge rst)
(!rst) ? (q<=0): (q<=d);
Click to expand...
yes, you will lose your job for complete inability to write logic like a human. fired for cause on the spot.

in a more serious tone, this style goes against typical coding styles. synthesis tools might complain or might even misinterpret the intent (unlikely). in short, there is no good reason why anyone would ever write this freakshow of a code.
 

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Let's wait on what FvM and dave_59 says on this.
 

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1. Please correct syntax errors
Code: 
always @(posedge clock or negedge rst)
q<= !rst ? 0 : d;

2. Similar to ThisIsNotSam, I'd prefer readable code. With this single line FF description, you'd start considerations, if it complies to the register code template.

3. At least Quartus recognizes the register description

 

    F

    fragnen

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Why will not the below code work? What Verilog LRM violation is there that the below code will not synthesize to a D-Flipflop?

always @(posedge clock or negedge rst)
(!rst) ? (q<=0): (q<=d);
 

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fragnen said:
Why will not the below code work? What Verilog LRM violation is there that the below code will not synthesize to a D-Flipflop?

always @(posedge clock or negedge rst)
(!rst) ? (q<=0): (q<=d);
Click to expand...
even if it was somehow LRM-compliant, it doesn't mean much. synthesizable RTL is a subset of the Verilog language. not everything that simulates becomes (useful) hardware.
 

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FvM said:
It's a conditional expression without an assignment (no LHS). Not valid statement.
Click to expand...
Sorry, it was missed. You are right.
--- Updated ---

ThisIsNotSam

What do you think on the FvM's code of flipflop as below?
always @(posedge clock or negedge rst)
q<= !rst ? 0 : d;
 

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not good. it does not follow typical templates. it raises questions where there should be none.
 

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What will be the pros and cons of using this below two codes for coding a synthesizable rtl for a flipflop with enable?

always @(posedge clock or negedge rst)
q<= !rst ? 0 : (enable? d : q);

Versus

always@(posedge clock or negedge rst)
if(!rst)
q<= 1'b0;
else if (enable)
q<=d;
 

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pros of style 1: none
cons of style 1: see post #10

pros of style 2: you don't get bullied by your colleagues during code review
cons of style 2: none
 

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