[SOLVED] concurrent assignment

In vhdl code for counter why do we assign signal count value to the output of counter after end process statement
for ex

counter code....
.......
end process;
count<=cout;

thank you

If count is an out of the entity then cout can't be connected to the out signal of the entity, therefore it's first assigned to count.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;

entity down_counter is
port (
clock: in std_logic;
reset: in std_logic;
load_enable: in std_logic;
load_data: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end;

architecture rtl of down_counter is
signal count: std_logic_vector(3 downto 0);
begin
process (clock, reset) begin
if reset then
count <= (others => '0');
elsif rising_edge(clock) then
if load_enable then
count <= load_data;
else
count <= count - 1;
end if;
end if;
end process;

output <= count;
end;


see this is a code... have a look at the last statement
value of signal count is assign to output

Yes, because count can't be directly connected to the out port of the entity as it's read in the process, so it is first assigned to output.

In hardware terms, signal count isn't but an alias of port output. According to classical VHDL syntax rules, you can't read an out port signal unless you define it as buffer instead of out. The restriction has been removed in VHDL 2008.

But you may prefer to keep an internal signal that is assigned to the out port in one place to clarify the data flow.

okkay but what is its significance?
can't we just write that code without using signal?
i mean directly output<= output +'1';
aslo if we take the above code then why the statement output<= count written after end process?

sumeet1990 said:

okkay but what is its significance?
can't we just write that code without using signal?
i mean directly output<= output +'1';

Click to expand...

Yes if you have a VHDL2008 compliant simulator and synthesis tool.

aslo if we take the above code then why the statement output<= count written after end process?

Click to expand...

because assigning it outside the process makes count show up on output without any extra delay and without dependency on signals in the sensitivity list.

Have you read any VHDL books prior to this? This stuff is covered in any reasonably good VHDL book.

Regards

well thank you
And yes I've read VHDL and i was aware of that explanation and just wanted to reassure it