concerns about simulation results on PN & NP folded casc

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allennlowaton

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Good day guys...

Please share your valuable ideas about this...
I was doing simulations about PN (PMOS-NMOS) folded cascode as well as NP(NMOS-PMOS) folded cascodes...
And the DC analysis interested me most...

I have some questions that seems to bother me...
(The Rd's and I's are current sources in my simulations)


Here are the schematics:


Here are my codes:


Here are the DC analyses:







Hope you can help me with these guys...

Thank you very much in advance...
 

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