concatenation operator in case statement

[rameshrai]

hi,

can i use the following in case statement?

with s1 & s0 select

where s1 and s0 are std_logic

I get error with this:

Select expression must be of a locally static subtype. Use -relax to allow expressions of a nonstatic subtype.

thanks for help

 

[imbichie]

Yes,
you can do something like this:

process(b0,b1,b2,b3)
   variable bcat : std_logic_vector(0 to 3);
begin
   bcat := b0 & b1 & b2 & b3;
   case bcat is
      when "0000" => x <= 1;
      when others => x <= 2;
   end case;
end process;

I got the example from some site

 

[TrickyDicky]

In VHDL 2008, this rule is relaxed, so concatenations are allowed.