[SOLVED] concatenation of two vhdl files

Status
Not open for further replies.
S

sumeet1990

Newbie level 5
Joined
Mar 29, 2013
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,348
hello all,
i am a new vhdl user
please help me find a link on how to concatenate two different files in vhdl into one new file
thank you.
 

How about using a text editor?

On a dos cmd line copy file1.vhd+file2.vhd newfile.vhd should work too.
 

FvM said:
How about using a text editor?

On a dos cmd line copy file1.vhd+file2.vhd newfile.vhd should work too.
Click to expand...

i think i misrepresented my question
see, i have a vhdl code whos output has to be used as input to an another vhdl code
so i want to connect two codes that way. please help me with that
thank you
 

Connecting VHDL entities has nothing to do with concatenating files. A VHDL compiler doesn't care i the design entities reside in one or multiple files.

You are asking about hierarchical VHDL designs where lower level entities are connected to an upper level by instantiating components. Each port signal of the component is connected to a signal in the instantiating entity.

I'm sure you'll find examples when searching for the respective keywords.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…