Computer Architecture: optimizing a comparator tree followed by array of subtractors

I'm attempting to design a circuit that takes 16 9-bit inputs, get the maximum, and then subtract each input from the maximum. Latency is not a constraint, however I'm concerned about throughput and area. Naively, I need a comparator tree of 15 comparators to get the maximum, and 16 subtractors to subtract each input from the maximum. Is there an efficient way to reuse the comparators to do the subtraction ? (especially if I use say 1 to 4 comparators only with an FSM to reduce my area). Can I combine both functionalities in one circuit efficiently?

Give me your thoughts

Hi,

As you are on PLDs forum, it is easy to write a behavioural code for this.

You can use 1 comparator if you want but you'll have to do the comparison 15 times. All data inputs would have to pass through a bus so don't forget the high-Z state.

Simple IF statements in a process should suffice.

First of all, you may create 16 registers of 9 bits, regt0 to regt15, and 2 comparator registers, compA and compB. Then you transfer the data from regt0 to compB and from regt1 to compA and save the data "greater than or equal to" the other data value in a back into compA. Then move the data in regt2 to regt15 to compB one at a time to compare with compA each time saving the "greater or equal" value back into compA. At the end, you'll have the greatest value in compA. You can then subtract each of data in regt0 to regt15 from the content of compA.

You can even keep track of the register with the greater data value in a 4-bit register and update it as you are doing the comparison.

I don't see anything that interesting. Maybe the max index could be tracked to remove one subtraction (max-max = 0). But that property seems hard to use without using more resources.

You can certainly reuse the logic units by having a clock rate that is a multiple of the input rate.