ece4afe
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Hello,
Please advise how to compute for the delay due to excess load capacitance, meaning higher capacitance value than the CL of the driving device.
For example in SRAM which has CL of 50pF, it is driving the data bus. Aside from the SRAM, the mcu, flash, buffers are also driving the data bus. These devices will be connected to the data bus pins of the SRAM and has input capacitance. The input capacitance of each device will be added since they are connected in parallel and will serve as load capacitance for the SRAM, which has large load capacitance than the rated Cl of it. Because of this extra capacitance, it will result to extra delay, other than specified in the datasheet. For example, if the SRAM has access time of 55ns, the actual access time should be 55ns + delay due to extra capacitance. My question is how to compute for this delay.
Thank you
Please advise how to compute for the delay due to excess load capacitance, meaning higher capacitance value than the CL of the driving device.
For example in SRAM which has CL of 50pF, it is driving the data bus. Aside from the SRAM, the mcu, flash, buffers are also driving the data bus. These devices will be connected to the data bus pins of the SRAM and has input capacitance. The input capacitance of each device will be added since they are connected in parallel and will serve as load capacitance for the SRAM, which has large load capacitance than the rated Cl of it. Because of this extra capacitance, it will result to extra delay, other than specified in the datasheet. For example, if the SRAM has access time of 55ns, the actual access time should be 55ns + delay due to extra capacitance. My question is how to compute for this delay.
Thank you