compressor based area-efficient low power 8x8 bit vedic multiplier.

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chshri94@gmail.com

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compressor based area efficient low power 8x8 bit vedic multiplier.

hai,
i designed a program for 8 bit vedic multiplier using compressors and carry save adder.check syntax is successfully completed.but while simulating for the testbench in xilinx 9.1i version getting the following warning and not getting the testbench waveforms.

code:
warning:simulator :29 no entity is not bound for inst saveadder waves.

what is the error? solution?
please provide the remedy for it as soon as possible

thanks and regards,
s.s
 

Re: compressor based area efficient low power 8x8 bit vedic multiplier.

It means that that the design "saveadder" is not bound. So all files within saveadder have not been compiled. Load the design in ISE. Check whether any component is missing. It will be shown by a question mark I suppose(from what I remember)
 

Re: compressor based area efficient low power 8x8 bit vedic multiplier.

hai,
all the files in save adder are bound as there is no question mark at them while simulating.
wts d problem?
please tell me.
thanks and regards
s.s

- - - Updated - - -

hai,
no question mark at any component.but the same response (same warning).please provide the other alternative of solving it
thanks and regards,
s.s
 

Re: compressor based area efficient low power 8x8 bit vedic multiplier.

I am sure that this error is because you have not compiled a particular module...Forget the question mark..I am not sure if that is the way ISE indicates it now..Check your hierarchy. Try changing the top module to "saveadder"..and renload the design..
 

Re: compressor based area efficient low power 8x8 bit vedic multiplier.

ISE 9.1i, what simulator did that use? I haven't used such an old version of ISE for so long I don't remember if they had ISIM yet or if that was using MXE (Modelsim Xilinx Edition). Can you clarify what simulator it's using and cut-n-paste into a post the entire transcript window when the design is being parsed up to and including the error message.
 

Re: compressor based area efficient low power 8x8 bit vedic multiplier.

i also hope that there is an error in saveadder program code.so can u help me to get the vhdl code for carry save adder of 8 bit .
 

Re: compressor based area efficient low power 8x8 bit vedic multiplier.

chshri94@gmail.com said:
xilinx ise 9.1i version
Click to expand...

I asked about the SIMULATOR you are using and not the ISE version. I even mentioned that you are using ISE 9.1i and that I don't know what simulator came packaged with that tool suite.

chshri94@gmail.com said:
i also hope that there is an error in saveadder program code.so can u help me to get the vhdl code for carry save adder of 8 bit .
Click to expand...

Where was I unclear, POST code, POST the transcript window. This is the last time I will ask the same questions, then I ignore you.
 

Re: compressor based area efficient low power 8x8 bit vedic multiplier.

full version of ise simulator sir,
 

Re: compressor based area efficient low power 8x8 bit vedic multiplier.

code:::::
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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:56:57 03/16/2015 
-- Design Name: 
-- Module Name:    projj - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity projj is
    Port ( a : in  unsigned(7 downto 0);
           b : in  unsigned(7 downto 0);
           o : out  unsigned(15 downto 0));
end projj;
 
architecture Behavioral of projj is
 
component faa is
   port(a:in std_logic;
       b:in std_logic;
         c:in std_logic;
         s:out std_logic;
         co:out std_logic);
end component;
component haa is
   port(a:in std_logic;
         b:in std_logic;
          s:out std_logic;
          c:out std_logic);
end component;
component comp63 is
         Port ( a : in  STD_LOGIC;
            b : in  STD_LOGIC;
           c : in  STD_LOGIC;
           d : in  STD_LOGIC;
           e : in  STD_LOGIC;
           f : in  STD_LOGIC;
           o1 : out  STD_LOGIC;
           o2 : out  STD_LOGIC;
              o3 : out  STD_LOGIC);
end component;
component comp53 is
         Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : in  STD_LOGIC;
           d : in  STD_LOGIC;
           e : in  STD_LOGIC;
           o1 : out  STD_LOGIC;
           o2 : out  STD_LOGIC;
           o3 : out  STD_LOGIC);
end component;
component comp43 is
         Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : in  STD_LOGIC;
           d : in  STD_LOGIC;
           o1 : out  STD_LOGIC;
           o2 : out  STD_LOGIC;
           o3 : out  STD_LOGIC);
end component;
component rcadder_8 is
          PORT( A1, B1 : IN unsigned (7 downto 0);
                Cforce : IN std_logic ;
                Sum1    : OUT unsigned(7 downto 0);
                Cout : OUT std_logic ) ;
                      end component;
component vedicmul is
          Port ( a : in  unsigned(3 downto 0);
                 b : in  unsigned(3 downto 0);
                 o : out  unsigned(7 downto 0));
end component;      
component saveadder is
           Port (a : in  unsigned(7 downto 0);
           b : in unsigned(7 downto 0) ;
           s : in  unsigned(7 downto 0);
              o1 : out unsigned(7 downto 0);
              o2 : out unsigned(7 downto 7));
                      
              
end component;
 
   signal p : unsigned(7 downto 0); 
    signal q : unsigned(7 downto 0);
    signal r : unsigned(7 downto 0);
    signal s : unsigned(7 downto 0);
    signal c : unsigned(7 downto 0);
    signal z : unsigned(7 downto 0);
    signal zs : unsigned (7 downto 0);
    signal zc : unsigned (7 downto 0);
    signal zc1 : unsigned(7 downto 0);
    signal o1 : unsigned (7 downto 0);
    signal u : unsigned(3 downto 0);
   signal u1 : unsigned(7 downto 0);
    signal v1 : unsigned(7 downto 0);
    signal v:unsigned(3 downto 0);
    signal zc2:unsigned (7 downto 0);
    signal zs2:unsigned (7 downto 0);
    signal zc3:unsigned (7 downto 0);
    signal o2:unsigned(7 downto 0);
    signal x:unsigned(3 downto 0);
    signal y:unsigned(3 downto 0);
    signal cout1:std_logic;
    signal cout2:std_logic;
    signal cin1 :std_logic;
    signal cout3:std_logic;
begin
 
 
cin1<='0';
cout1 <=zc(7);
cout2<= zc2(7);
 
u(3 downto 0) <= o1(7 downto 4);
v(3 downto 0)<= p(7 downto 4);
v1 <= '0'&'0'&'0'&'0' &v;
u1 <= "0000"&u;
x(3 downto 0)<=o1(3 downto 0);
y(3 downto 0) <= p(3 downto 0);
zc1 <= zc(6)&zc(5)&zc(4)&zc(3)&zc(2)&zc(1)&zc(0)&'0';
 
zc3 <= zc2(6)&zc2(5)&zc2(4)&zc2(3)&zc2(2)&zc2(1)&zc2(0)&'0';
 
g1:vedicmul port map(a(3 downto 0),b(3 downto 0),p(7 downto 0));
g2:vedicmul port map(a(3 downto 0),b(7 downto 4),q(7 downto 0));
g3:vedicmul port map (a(7 downto 4),b(3 downto 0),r(7 downto 0));
g4:vedicmul port map(a(7 downto 4),b(7 downto 4),s(7 downto 0));
g5:saveadder port map(q(7 downto 0),r(7 downto 0),v1(7 downto 0),zs(7 downto 0),zc(7 downto 0));
g6:rcadder_8 port map(zs(7 downto 0),zc1(7 downto 0),cin1,o1(7 downto 0),cout1);
g7:saveadder port map(u1(7 downto 0),s(7 downto 0),z(7 downto 0),zs2(7 downto 0),zc2(7 downto 0));
g8:rcadder_8 port map(zs2(7 downto 0),zc3(7 downto 0),cout2,o2(7 downto 0),cout3);
o <=  o2&x&y;
 
end Behavioral;
 
Last edited by a moderator:

Re: compressor based area efficient low power 8x8 bit vedic multiplier.

Ugh, why don't they teach VHDL correctly and tell you to use the correct packages!

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;

You can't use numeric_std along with std_logic_arith and std_logic_unsigned. The later 2 are synopssy packages that are not part of the IEEE VHDL standard. Remove them from your design.

Beyond that, what am I supposed to help you with in your code.... There is no explanation as to what is your problem (besides being totally clueless as to how to ask a question)

I'm getting really tired of having to pry information from posters, who don't formulate complete answerable questions. I finished with this thread
 

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