The blocks you are looking for a better done by coding them in VHDL as behavioral RTL. I wouldn't build a structural netlist in VHDL using primitives or even higher level components like adders, multiplexers, and decoders like you seem to want to do. You need to drop the schematic mindset if you want to use an HDL. I would invest more time in learning VHDL and drop the schematic entry entirely.
I haven't entered any portion of an FPGA design in schematics for close to 20 years and I don't miss it. I can see the benefit of having a block diagram for a top level file, but even then I'd rather it just be a VHDL/Verilog top level RTL module that I can read/modifiy in a text editor like VIM. (personally I can type a whole lot faster than moving a mouse around connecting stuff)