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'Complexity crisis' roils EDA, analyst says
By Richard Goering, EE Times
Jun 2, 2003 (8:46 AM)
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ANAHEIM, Calif. — The 100 million gate complexity made possible by 90 nanometer processes caused "panic" among power EDA users last year, and will fuel the demand for electronic system level (ESL) tools, according to Gary Smith, chief EDA analyst at Gartner Dataquest. Smith spoke at Dataquest's Sunday (June 1) briefing at the Design Automation Conference here.
Also at the briefing, Bryan Lewis, chief analyst for ASIC, system-on-chip (SoC) and FPGA research at Gartner Dataquest, predicted a 2003 upturn for ASICs, ASSPs and FPGAs. But ASIC design starts continue to drop, he said.
Wally Rhines, Mentor Graphics CEO and EDA Consortium (EDAC) chair, opened the briefing on an optimistic note by predicting a "uniquely different" recovery for the EDA and semiconductor industries. What's different, he said, is that unlike previous recessions, the most recent downturn left plenty of leading-edge fab capacity available.
"Unlike other recoveries, you'll see a prolonged period of design activity, because we're not going to run out of leading edge capacity for a long time," he said. This will benefit EDA, Rhines said, because advanced processes will push the need for customers to purchase new tooling.
Rhines cited EDAC figures showing that EDA revenues were down seven percent annually in 2001, the first annual decline since EDAC started keeping records. But most of this decline was in services, he said.
Smith said EDA actually grew 3.3 percent in 2002, not counting services, and he said Dataquest expects a 7.8 percent increase this year, to a total of $2.98 billion. But he said he doesn't expect double-digit growth until 2005, "when ESL tools hit the market en masse."
Smith said power users are facing their first-ever "design gap" because they can't come close to using the 100-million gate capacity of 90 nm processes. If ESL comes on line by 2005, that should provide a 60 percent boost in productivity, he said. But the real gains will come later on, he said, when ESL and design reuse methodologies combine to allow the reuse of multi-million gate blocks.
ESL, Smith said, is hardware/software co-design and verification. The ESL flow encompasses behavioral design, hardware/software partitioning and architectural design. But silicon virtual prototyping is needed to make it all work, and here Smith had some words of criticism. "The EDA vendors have continued for one more year to totally miss the mark," he said.
Smith pointed to Magma Design Automation, Monterey Design Systems and Tera Systems as companies who have brought new silicon virtual prototyping technology to this year's DAC. He mentioned the Axis Systems XoC and Cadence Design Systems Incisive products as key developments in hardware/software co-verification.
Daya Nadamuni, analyst at Gartner Dataquest, also called for ESL as she discussed trends in innovation in electronic design. She said that innovation will be driven by advances in design, and will depend on architectural breakthroughs. "A move into ESL design and methodology will become a must for today's SoCs," she said.
Lewis said the overall semiconductor industry grew by 1.6 percent in 2002, with 8.3 percent growth expected in 2003. But the market won't really take off until capital expenditures improve, he noted.
Lewis said that ASIC revenues declined 4 percent in 2002 and will grow 6.1 percent in 2003. But ASSPs grew 5.4 percent in 2002 and will grow 10.3 percent in 2003. FPGAs declined 12.2 percent in 2002 but will grow 14.3 percent in 2003, according to Lewis.
There were 3,500 to 4,000 "bona fide" ASIC design starts in 2002, Lewis said. But he displayed a chart predicting a continuing decline in ASIC design starts, from over 11,000 in 1997 to under 4,000 in 2006. ASSP design starts, however, remain relatively stable throughout this period. And Lewis noted that the overall number of gates is not decreasing.
"The worst is behind us," Lewis said. "It is our belief that the ASIC market is not dead."
By Richard Goering, EE Times
Jun 2, 2003 (8:46 AM)
URL: **broken link removed**
ANAHEIM, Calif. — The 100 million gate complexity made possible by 90 nanometer processes caused "panic" among power EDA users last year, and will fuel the demand for electronic system level (ESL) tools, according to Gary Smith, chief EDA analyst at Gartner Dataquest. Smith spoke at Dataquest's Sunday (June 1) briefing at the Design Automation Conference here.
Also at the briefing, Bryan Lewis, chief analyst for ASIC, system-on-chip (SoC) and FPGA research at Gartner Dataquest, predicted a 2003 upturn for ASICs, ASSPs and FPGAs. But ASIC design starts continue to drop, he said.
Wally Rhines, Mentor Graphics CEO and EDA Consortium (EDAC) chair, opened the briefing on an optimistic note by predicting a "uniquely different" recovery for the EDA and semiconductor industries. What's different, he said, is that unlike previous recessions, the most recent downturn left plenty of leading-edge fab capacity available.
"Unlike other recoveries, you'll see a prolonged period of design activity, because we're not going to run out of leading edge capacity for a long time," he said. This will benefit EDA, Rhines said, because advanced processes will push the need for customers to purchase new tooling.
Rhines cited EDAC figures showing that EDA revenues were down seven percent annually in 2001, the first annual decline since EDAC started keeping records. But most of this decline was in services, he said.
Smith said EDA actually grew 3.3 percent in 2002, not counting services, and he said Dataquest expects a 7.8 percent increase this year, to a total of $2.98 billion. But he said he doesn't expect double-digit growth until 2005, "when ESL tools hit the market en masse."
Smith said power users are facing their first-ever "design gap" because they can't come close to using the 100-million gate capacity of 90 nm processes. If ESL comes on line by 2005, that should provide a 60 percent boost in productivity, he said. But the real gains will come later on, he said, when ESL and design reuse methodologies combine to allow the reuse of multi-million gate blocks.
ESL, Smith said, is hardware/software co-design and verification. The ESL flow encompasses behavioral design, hardware/software partitioning and architectural design. But silicon virtual prototyping is needed to make it all work, and here Smith had some words of criticism. "The EDA vendors have continued for one more year to totally miss the mark," he said.
Smith pointed to Magma Design Automation, Monterey Design Systems and Tera Systems as companies who have brought new silicon virtual prototyping technology to this year's DAC. He mentioned the Axis Systems XoC and Cadence Design Systems Incisive products as key developments in hardware/software co-verification.
Daya Nadamuni, analyst at Gartner Dataquest, also called for ESL as she discussed trends in innovation in electronic design. She said that innovation will be driven by advances in design, and will depend on architectural breakthroughs. "A move into ESL design and methodology will become a must for today's SoCs," she said.
Lewis said the overall semiconductor industry grew by 1.6 percent in 2002, with 8.3 percent growth expected in 2003. But the market won't really take off until capital expenditures improve, he noted.
Lewis said that ASIC revenues declined 4 percent in 2002 and will grow 6.1 percent in 2003. But ASSPs grew 5.4 percent in 2002 and will grow 10.3 percent in 2003. FPGAs declined 12.2 percent in 2002 but will grow 14.3 percent in 2003, according to Lewis.
There were 3,500 to 4,000 "bona fide" ASIC design starts in 2002, Lewis said. But he displayed a chart predicting a continuing decline in ASIC design starts, from over 11,000 in 1997 to under 4,000 in 2006. ASSP design starts, however, remain relatively stable throughout this period. And Lewis noted that the overall number of gates is not decreasing.
"The worst is behind us," Lewis said. "It is our belief that the ASIC market is not dead."