[SOLVED] compiling verilog a file in cadence

[preethi19]

Hi i have the knowledge of creating a schematic and running analysis but now i have a verilog a file and i have no idea how to run it and observe the results. Currently i am only able to view the file. How can i get the symbol or results by running the verilog a code in cadence? Can anyone kindly let me know the way for it. Thanks a lot!!!

 

[dick_freebird]

When you create the veriloga view (copy from symbol) you
should also spawn a text editor window to work the veriloga
code. Save/quit there, should cause syntax- / error-checking.
But compilation happens at simulation run time (you should
see some messages about veriloga to C compilation go past,
right after model include-chain readin, once per simulator
session encountering a veriloga or a changed veriloga; after
it has done it once clean, it doesn't need to repeat until the
next session).

To run it you'd create a simulation testbench, place the
symbol of interest, make sure veriloga takes precedence in
your search / stop lists (or use config view simulation
testbench, if you need to assert a mix of veriloga and
schematic based views). Remember to place trivial resistors
at veriloga ports if you want to see port currents, unless
you are sophisticated enough to figure out how to get the
currents mapped clean to the ports themselves; I never
did figure that out, but the analogLib resistor will do that
because it must.