Compile all the files once only for all round of simulations

syedshan · May 21, 2013

Hi all

I tried to explain the Title itself...
Actually I am desining osmething communicating with the DDR3 for that I use the MIG, hence there are loads of files that I need to compile, which takes quite a lot of time.
Then after that simulation itself takes time.

Hence what I want is to compile the files that are not subject to any change (i.e. which are made by Xilinx IP core, etc.) only once, and later just use the compiled file etc. of this when I load in the modelsim. Is there any way to do that.

Note that I am using .do file for running the modelsim from ISE.

TrickyDicky · May 21, 2013

stick the MIG and DDR code in it's own directory. Create the work library in modelsim:

vlip work;

compile all of the DDR model and MIG code

vcom/vlog filea.vhd
--etc

now in your working directory, do the following command:

vlib MIG_lib
vmap MIG_lib /somewhere/MIG_lib/work

then vcom/vlog your working files.

no need to compile all of the DDR and MIG as they shouldnt be changing.

syedshan · May 22, 2013

Thank you for your response...

I tried many times and followed different steps, ultimately I think this is the best, but even then it does not work....

Lets say the Main folder is

C:/.../prj_UD_ver2

2. Then MIG files are in C:/.../prj_UD_ver2/src/RTL/MIG_files
3. I ddid following steps.

Code:

cd C:/.../prj_UD_ver2/src/RTL/MIG_files
vlib work
vmap work C:/.../prj_UD_ver2/src/RTL/MIG_files/work
then vcom/vlib all....

4. Now these are the run.do file that I ran.(not that I invoke it thru ISE, giving the proper .do file location etc.)

Code:

#change back to simulation folder
cd C:/.../prj_UD_ver2/src/sim

vmap unisim C:/Xilinx/13.2/ISE_DS/ise/vhdl/mti_se/6.5c/nt64/unisim

vlib MIG_lib;
vmap MIG_lib C:/.../prj_UD_ver2/src/RTL/MIG_files/work;

vlib work;
vmap work C:/.../prj_UD_ver2/src/sim/work;
vcom other simulation and other RTL files (except ofcourse MIG)

vsim -t fs -novopt +notimingchecks -L unisim work.sim_tb_top glbl

...
..

5. But at vsim location I get the following errors, where as they are already compiled in the the MIG_lib

# ** Warning: (vsim-3473) Component instance "u_clk_ibuf : clk_ibuf" is not bound.
# Time: 0 fs Iteration: 0 Region: /sim_tb_top/u_ip_top File: C:/Users/EIK/Desktop/Test_Code/prj_UD_withdata_map_beta_ver2/src/rtl/mig_des_MT41J256.vhd
# ** Warning: (vsim-3473) Component instance "u_iodelay_ctrl : iodelay_ctrl" is not bound.
# Time: 0 fs Iteration: 0 Region: /sim_tb_top/u_ip_top File: C:/Users/EIK/Desktop/Test_Code/prj_UD_withdata_map_beta_ver2/src/rtl/mig_des_MT41J256.vhd
# ** Warning: (vsim-3473) Component instance "u_infrastructure : infrastructure" is not bound.
# Time: 0 fs Iteration: 0 Region: /sim_tb_top/u_ip_top File: C:/Users/EIK/Desktop/Test_Code/prj_UD_withdata_map_beta_ver2/src/rtl/mig_des_MT41J256.vhd
# ** Warning: (vsim-3473) Component instance "u_memc_ui_top : memc_ui_top" is not bound.
# Time: 0 fs Iteration: 0 Region: /sim_tb_top/u_ip_top File: C:/Users/EIK/Desktop/Test_Code/prj_UD_withdata_map_beta_ver2/src/rtl/mig_des_MT41J256.vhd

- - - Updated - - -

Hence simulation did not proceed furhter as expected,

imbichie · May 22, 2013

The errors seems like the modules clk_ibuf, odelay_ctrl, infrastructure and memc_ui_top are not compiled yet or may be the compilation order is not proper.

You can compile these modules/files by include it in the *.do file, if the files are already there in the *.do file then you can change the compilation order according to the module instantiation.

If any of the modules are Xilinx primitive, then you need to map the Xilinx libraries like Simprim, Unisim, XilinxCorelib to the ModelSim

syedshan · May 22, 2013

Thank you for reply...

Can you verify, are the steps
I have seen in the MIG_RTL/work folder (to which to MIG_lib is mapped) that the infrassctrue is copiled there, similarly memc_uip_top as well.

I have used the unisim already mapped ( I think it is enough for Blk memory and FIFO) since I never ised xilinxCorelib as far as I remember, but even then it worked( I mean FIFO and ROM)

imbichie · May 22, 2013

The thing is that have you compiled these modules/files clk_ibuf, odelay_ctrl, infrastructure and memc_ui_top, before the compilation of the mig_des_MT41J256.vhd file, because when the ModelSim is tries to compile the mig_des_MT41J256.vhd file the modules clk_ibuf, odelay_ctrl, infrastructure and memc_ui_top are not in the work library.

You should compile these clk_ibuf, odelay_ctrl, infrastructure and memc_ui_top modules/files before the compilation of mig_des_MT41J256.vhd

syedshan · May 22, 2013

again the errors

Loading work.mig_des_mt41j256(arch_mig_des_mt41j256)
# ** Warning: (vsim-3473) Component instance "u_clk_ibuf : clk_ibuf" is not bound.
# Time: 0 fs Iteration: 0 Region: /sim_tb_top/u_ip_top File: C:/Users/EIK/Desktop/Test_Code/prj_UD_withdata_map_beta_ver2/src/rtl/mig_des_MT41J256.vhd
# ** Warning: (vsim-3473) Component instance "u_iodelay_ctrl : iodelay_ctrl" is not bound.
# Time: 0 fs Iteration: 0 Region: /sim_tb_top/u_ip_top File: C:/Users/EIK/Desktop/Test_Code/prj_UD_withdata_map_beta_ver2/src/rtl/mig_des_MT41J256.vhd
# ** Warning: (vsim-3473) Component instance "u_infrastructure : infrastructure" is not bound.
# Time: 0 fs Iteration: 0 Region: /sim_tb_top/u_ip_top File: C:/Users/EIK/Desktop/Test_Code/prj_UD_withdata_map_beta_ver2/src/rtl/mig_des_MT41J256.vhd
# ** Warning: (vsim-3473) Component instance "u_memc_ui_top : memc_ui_top" is not bound.
# Time: 0 fs Iteration: 0 Region: /sim_tb_top/u_ip_top File: C:/Users/EIK/Desktop/Test_Code/prj_UD_withdata_map_beta_ver2/src/rtl/mig_des_MT41J256.vhd
# Refreshing C:\Users\EIK\Desktop\Test_Code\prj_UD_withdata_map_beta_ver2\src\sim\work.design_pack(body)
# Loading work.design_pack(body)
# Refreshing C:\Users\EIK\Desktop\Test_Code\prj_UD_withdata_map_beta_ver2\src\sim\work.top_uwpi(behavioral)
# Loading work.top_uwpi(behavioral)
# Refreshing C:\Users\EIK\Desktop\Test_Code\prj_UD_withdata_map_beta_ver2\src\sim\work.data_map_top(behavioral)
# Loading work.data_map_top(behavioral)
# Refreshing C:\Users\EIK\Desktop\Test_Code\prj_UD_withdata_map_beta_ver2\src\sim\work.rom_table(rom_table_a)
# Loading work.rom_table(rom_table_a)
# Loading xilinxcorelib.blk_mem_gen_v6_2(behavioral)
# Loading xilinxcorelib.blk_mem_gen_v6_2_mem_module(mem_module_behavioral)
# ** Note: Block Memory Generator CORE Generator module loading initial data...
# Time: 0 fs Iteration: 0 Instance: /sim_tb_top/u_ip_top/u_top_uwpi/inst_data_map/inst_addrom/u0/native_mem_module/mem_module
# ** Error: (vsim-7) Failed to open VHDL file "rom_table.mif" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 fs Iteration: 0 Instance: /sim_tb_top/u_ip_top/u_top_uwpi/inst_data_map/inst_addrom/u0/native_mem_module/mem_module
# ** Fatal: (vsim-7) Failed to open VHDL file "rom_table.mif" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 fs Iteration: 0 Process: /sim_tb_top/u_ip_top/u_top_uwpi/inst_data_map/inst_addrom/u0/native_mem_module/mem_module/line__3300 File: C:/Xilinx/13.2/ISE_DS/ISE/vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_2.vhd
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./run.do PAUSED at line 31

The MIG_IPs library shows that it has infrastrucre, iodelay, and others compiled.... Then why not working properly

What is rom_table.mif, note that rom_table is a ROM generated with xilinx core and hence its library xilinxcoelib also mapped already...!!!

waiting madly

imbichie · May 22, 2013

syedshan said:
What is rom_table.mif, note that rom_table is a ROM generated with xilinx core and hence its library xilinxcoelib also mapped already...!!!
[/B]

*.mif is nothing but the Memory Initializing File. When you are generating the ROM module, you can initialize the ROM using the *.coe file.Then after the ROM generation there will be a *.mif file for the ROM module

- - - Updated - - -

For sample *.coe you can google it

syedshan · May 22, 2013

Pardon me if this iterates you,

but yes I got to your point and even found and saw the .mif files for the respective cores.
Even they exist at location.

I Also want to verify the .do file and the the flow that I am following.

Bests,
Shan

TrickyDicky · May 22, 2013

you have ; on the end of some lines in the TCL file. you dont use ; on the end and may be causing the vmap to fail.

and this line "vcom other simulation and other RTL files (except ofcourse MIG)" need to be commented out.

Compile all the files once only for all round of simulations

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