compensation..........attention needed

[Ni1009]

Dear friends ,

can some one share some details about type-3 compensation simulation for DC-DC development. I have simulated type-3 given in intersil document which i have attached. But whatever i have simulated is bit revese and stange also. So please can some one eloborate/help on this.

Ni

 

[LvW]

Dear friends ,
can some one share some details about type-3 compensation simulation for DC-DC development. I have simulated type-3 given in intersil document which i have attached. But whatever i have simulated is bit revese and stange also. So please can some one eloborate/help on this.
Ni

Hi Ni1009,

I don`t know if it helps - but be careful with the information contained in the Intersil note. I did not check the formulas/drawings for type iii compensation, but I found out that there is at least one error in the type ii drawing (R1C1 must be R1C2). More than that, it is to be noted that the -180 phase shift due to inverting operation is not considered. For both compensation schemes C2 must be larger than C1.
Please note that your gain response shows a positive slope which indicates instability.
My recommendation: Recalculate the parts values.

 

[Ni1009]

Dear LvW,

thank you for the reply. Infact i have reclaculated making sure about C1, C2 terms in the equation and found the same waveforms for new set of values. Let me tell you that i am using a non-ideal opamp model (Verilog-A) created using model writer and have set some gain(43) and pole frequency (0). Is these factors causing any variaations.

Also could you pls tell me how to change the slope of gain to -ve.


Regards
Ni1009

 

[LvW]

Let me tell you that i am using a non-ideal opamp model (Verilog-A) created using model writer and have set some gain(43) and pole frequency (0).

What does this mean? 43 dB? And Fpole=0 Hz ?
Please use always units - otherwise figures are meaningless.

Also could you pls tell me how to change the slope of gain to -ve.

When the simulated gain slope (ac analysis) is positive, this indicates instability of the circuit. You must try to find the reason for instability!

 

[Ni1009]

Dear LvW,

please find the verilog-A code which i have been using. i have set a gain of 32db and pole freq of 0 for opamp.

********************************************************************
// FUNCTION: Ideal/Non-ideal OpAmp
//
// GENERATED BY: Cadence Modelwriter 2.30
//
// Description: Universal Opamp
// vin_p - positive or non-inverting input
// vin_n - negative or inverting input
// vout - single ended output
// This model is an example, provided "as is" without express or
// implied warranty and with no claim as to its suitability for
// any purpose.
//
// Known problem:
// The output waveform displays ringing when the second order
// pole
// is specified.
//
// PARAMETERS:
// dcopt = DC operating point, or t=0 voltage [V]
// gain = Open loop voltage gain, or DC voltage gain
// ibias = Input bias current, the value is the same for
// both inputs [A]
// pole_freq = Dominant pole frequency, or first corner
// frequency, eg. point where gain begins to roll of by 6 dB /
// octave [Hz]
// pole_sec = Second pole frequency, point at which gain
// rools off more steeply [Hz]
// rin = Differential input resistance, or resistance
// measured between both inputs [ohms]
// rout = Single ended output resistance [ohms]
// slewn = Maximum negative output voltage slope [-V/S]
// slewp = Maximum positive output voltage slope [V/S]
// vin_offset = Input offset voltage, the voltage required for
// 0 volts output [V]
// vsoft = Output soft clipping point, measured from the
// supply rails [V]
//

`include "discipline.h"
`include "constants.h"

// model opamp - Non Ideal OpAmp Model


module opamp (vout, vin_p, vin_n, vspply_p, vspply_n );
inout vin_p , vin_n;
inout vspply_p, vspply_n;
output vout;
electrical vin_p, vin_n, vout, vspply_p, vspply_n;


parameter real gain = 43 exclude 0.0;
parameter real pole_freq = 0.0;
parameter real rin = 12.0K exclude 0.0;
parameter real rout = 75.0;
parameter real ibias = 0.0n;
parameter real vin_offset = 100u;

real c1, r1;
real r_rout,gm_nom, vin_val;
real vmax_in_p, vmax_in_n, iin_max_p, iin_max_n;
electrical cout, vref;


analog begin

@(initial_step or initial_step("dc", "ac", "tran", "xf")) begin
r1 = gain;
gm_nom = 1.0;
c1 = 1/(`M_TWO_PI * pole_freq * gain);
r_rout = rout;

end

vin_val= V(vin_p, vin_n) + vin_offset;

// ------ Vref is at Virtual Ground
V(vspply_n, vref) <+ V(vspply_n) + (0.5*(V(vspply_p)-V(vspply_n)));

// ------ Input Stage
I(vin_p, vin_n) <+ vin_val / rin;
I(vref, vin_p) <+ ibias;
I(vref, vin_n) <+ ibias;

// ------ GM stage
I(vref, cout) <+ gm_nom*vin_val ;
// ------ Dominant Pole.
I(cout, vref) <+ ddt(c1*V(cout, vref));
I(cout, vref) <+ V(cout, vref)/r1;

// ------ Output Stage.

I(vref, vout) <+ V(cout, vref)/r_rout;
I(vout, vref) <+ V(vout, vref)/r_rout;
end
endmodule

********************************************************************



and regarding stability i am simulating only error amplifier with type-3 compensation arrange ment and i had already attached the waveforms in my previous post. please can you help me make more clear about this. I hope i have provided all details possible.


Ni1009

 

[LvW]

I do not use verilog-A (and I am not familiar with it) - but I detect the following in your input code:

parameter real gain = 43 exclude 0.0;
parameter real pole_freq = 0.0;
parameter real rin = 12.0K exclude 0.0;
parameter real rout = 75.0;
parameter real ibias = 0.0n;
parameter real vin_offset = 100u;

Questions:
Why a gain of only 43 (32 dB)?
Why rin only 12 kohms ?

Problem: Vin_offset=100u

Since your circuit does not have any dc feedback, you run into operating point problems. At first, try to set Vin_offset=0 and increase the open loop gain to at least 80 dB. Perhaps this solves the problem.

Additional question: Are sure that the feedback path is connected to the inverting opamp terminal?

Added after 5 hours 50 minutes:

Hi NI1009,

there is another point which confuses me: You have specified a finite dc gain and at the same time a pole at f=0 Hz.
I don't know if and how verilog accepts such conflicting specifications. Or did I misunderstand something?

 

[Ni1009]

Hi LvW,


Yes i have tried keeping high gain around 80db, offset as 0 and even tried reducing rin, but no luck. I am posting my schematic so that you can help me fix it further.

Ni1009

 

[LvW]

Hi LvW,

Yes i have tried keeping high gain around 80db, offset as 0 and even tried reducing rin, but no luck. I am posting my schematic so that you can help me fix it further.
Ni1009

* Reducing rin ???
* Check your operating (bias) point, because I see dc voltage sources at the input (Vref, Vss).