Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
This looks wrong. I have also done gm/id vs. Vgs for N and P MOS transistors in 16nm TSMC and I don't see this behavior. In my case both types of transistors see a rising trend in gm/id as Vgs decreases and reach a value of about 30 for Vgs=0. I have not done this for technologies below 16nm.
thank you. do you have FINFET 16nm TSMC library with independent gates now ? can you send for me?
…………..
no. i use bsim from berkeley. did you plot curves in finfet technology?
…………..
i plotted curves in 55nm finfet technology. did you plot curves in finfet technology?
If you mean if you can find finfet models - you can't unless you work with a design kit for that technology.
If you mean finding information about finfet devices - well, easiest is to search the internet.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.