[SOLVED] Comparing two user defined type signals in VHDL

[biju4u90]

I define two signals present_state and next_state as below in VHDL.

type state is (reset_state, AA_55_state, FF_00_state, ring_1_state, ring_0_state);
signal present_state : state;
signal next_state : state;

In the code, I want to check whether present_state is equal to next_state or not and assign a value to count accordingly.

when I give like
if (clk = '1' and clk'event) then
if ((present_state) = (next_state)) then
count <= '0'


its working perfectly. But if I write like

if (clk = '1' and clk'event) then
if ((present_state) /= (next_state)) then
count <= '0'

I don't get any error, But count doesn't get the assiged value.
Can't I use the "not equal to" operator for comparing two user defined type signals?

 

[amit.kumar11]

Hi,

You can use not equal to operator. In your case both present_state and (next_state) are equal, so your condition of " if ((present_state) /= (next_state))" is not meeting. That's why count is not getting assigned value as "0".

 

[biju4u90]

Nopes. I assign the next_state value to present_state. So my present_state signal will have a delay of 1 clock cycle compared to next_state signal. I am comparing these signals at this difference point!!

- - - Updated - - -

Oh...you were correct. It was a confusion from my side. Got it cleared now. Thanx for the help