Comparator with hysteresis - convergence problem

Hi.

I'm working on a school project, which aims to design an cell voltage supervisor according to the datasheet. I've encountered this very basic problem. One of the functions of the device is to detect the undervoltage, if the cell voltage falls below 2.3 V. The discharge MOSFET is then turned OFF. It should be turned ON again, if the cell voltage rises above some voltage. Let's say this voltage is 3.0 V. So I designed a simple comparator using the ABM models using this equations:

LIMIT(1MEG*V(%IN1,%IN2),5,0) for the op-amp
IF(V(%IN)>0,3,2.3) for the feedback (connected between op-amps output and IN2). This should simulate the hysteresis. It works perfectly in the block I designed for detecting overvoltage, but in this case, PSpice reports convergence problem. I also try to design simple comparator with ideal op-amp and resistors, instead of using ABMs, but the result was the same. Also I found out, that if I increase the threshold voltages of the comparator, it works. For example, IF(V(%IN)>0,4.5,4) works fine.

Can anybody help me solve this?
Thanks.

The problem remains vague without a complete simulation circuit.

Ok, this is the circuit.

Wrong sign of hysteresis function, I think. It's like negative feedback with discontinuity, causing permanent oscillations.

Ok, my bad. I tried some stuff and I figured out, that I have to solve another problem. Comparator now works fine, but if I connect som logic gate, e.g. OR, there comes the convergence error again. Any ideas how to fix this?

Convergence problems are common in Spice. Here are some sources on solving that problem.