Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Comparator topologies

kimmyo6

Newbie
Newbie level 2
Joined
May 27, 2024
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
23
Hello,

What type of comparator topology is this? I though that at least the comparator itself was dynamic, but after a review on several topologies, I'm confused. Hybrid?

1721775767216.png


Thanks.
 
The left side looks like a long-tail pair operating as a normal differential detector.

The cross-biased arrangement M6 M7 creates an SR flip-flop. 'Latch' at M12 describes a storage function which preserves the state (hi or lo) coming from the left whenever M12 operates several transistors which perform storage.

The buffer IC's provide a few more mA if needed.

This comparator is able to act as a logic probe. One brief pulse (charge of state) may go unnoticed however this system serves to indicate one or more such pulses did occur.
 

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top