theguardian2001
Junior Member level 3

Hi everyine! I am currently trying to implement and test a comparator, which consist of a preamplifier with two stages: folded cascode and common-source, and a pmos-latch. When I am running a dc simulation while keeping an inverting input constant and sweeping non-inverting one with a slow step, I see that negative and positive outputs staying at the same level for some small range of input voltage sweep, which, probably indicates an offset. However, after adding a 10mV source between inverting and non-inverting inputs I see that characteristics simply shift while leaving the gap (offset) between them unchanged. That causes latch outputs to behave as one sees in the first figure. If I try to latch amplifier's outputs firstly to prevent their overlap, and then use these "latched" outputs to apply them to another latch, I reduce the offset seen considerably but see the oscillations as in the second figure. Running the transient analysis on the same circuit and applying a pulse to the non-invertiung input gives reasonable graphs.
I am confused with interpreting the results I am seeing. Are these oscillations one sees in the second figure comes from dc simulation itself (maybe it can not resolve such fast transitions?), or it might indicate a meta-stability?
I am confused with interpreting the results I am seeing. Are these oscillations one sees in the second figure comes from dc simulation itself (maybe it can not resolve such fast transitions?), or it might indicate a meta-stability?