Comparator: preamplifier, decision, postamplification

[Steven De Bock]

Hello, I've already asked in another topic about a 3 stage comparator which has been described in the book "CMOS circuit design, layout and simulation" by R.J.Baker. But I thought it would be much more interesting to start a new topic for this kind of comparator.

The comparator described, exists out of 3 stages being a preamplifier, a decision stage and a postamplification. Schematics for these stages are down below.

The biggest problem I have with this comparator is how to dimension the transistors in the decision circuit? I choose the dimensions of the transistors in the decision stage the same since I don't want any hysteresis, but what W/L should I choose in order to optimize propagation speed? Are there any other concers in this kind of comparator?

Hints, references to other papers would be highly appreciated to!!
Thank you very much!

 

[pkalavakuru]

Hi u can keep the dimensions same for all ttansistor in Decision circuit but to get fast propagation speed u have to keep the length longer..10 times ur gate lenght(basedon ur Technology)

ciao

 

[Steven De Bock]

Ok, thank you!

But could you explain to me why increasing the length would improve propagation speed? Far as far as I know increasing length, only increases parasitic capacitances.

Can you give me an idea why you state that I should chose my length, 10 times the minimal length?

Thanks I appreciate it!

 

[Vamsi Mocherla]

Dear Steve,

For high speed design, we need to make sure that the first stage has less gain(in fact this gain is limited by the resolution required and also the input referred offset) in order to have a low impedance node in the middle.

The latch transistors should be sized such that they have smaller parasitics. T1 to T4 are sized for speed where the 1/gm of the transistors of this transitors determines the delay/speed. Also, the gm of this transistors is determined by the current.

You can actually forgo the third stage, because this stage by itself has systematic offset. In order to avoid this, you can make this stage differential. The input transistors of this stage need to have a smaller VGST and hence the sizing of those transistors. The other limit would still be introduction of the poles in the expected frequency response at their gate points.

I tried to put the synopsys of my ideas. Please excuse if the are not clear.

 

[rfic]

the last stage is self-biased amplifier ;

how to find a reference that describes the self-biased amplifier ?

 

[Steven De Bock]

Clearly there is some interest in this kind of amplifier, since I received the following query in my mailbox:

-----------------------------

Enquiry: Comparator: preamplifier, decision, postamplification
Do you have the layout for this circuit.
You would be helping me a great deal.
Also what dimensions did you use for each transistor so as to avoid parasitic
capacitance.
also for increased gain and still maintaining its main characteristic which is
high speed.
Pls could you email me if it is no trouble for you.

Thanks a bunch.

----------------------------

I'll be posting my findings on this comparator and update the schematics if I get clearance. The schematics are finished, but I'm afraid layout won't be part of it...

In the meanwhile remarks or experiences from other EDAboard users are welcome!

 

[yellff]

Vamsi Mocherla,that is sound good.

 

[n1cm0c]

Hi,

In your first schematic the PMOS should be connected as current mirrors to the output PMOS pair.

At the first stage you are designing for large gm (NMOS diff input gm) and low offset. By referring offset to the input you'll see that you'll want the highest
gm from the input NMOS pair that you can get for your current budget. You'll
then design the NMOS input devices for low overdrive (this also helps for the
input offset).

The PMOS mirror load should have a gm about 3 times the gm of the NMOS input
pair. You are designing for low offset and you also want to maximize the
frequency of the pole here. Higher gm by itself won't push the pole frequency
up, because the gate capacitance also rises... Given the current, set by the
input pair bias sink, you can only play with W/L until you get the fastest
possible time constant here. Then you'll have to raise L of the PMOS until
your input referred offset is within specs. If you trust your foundry model start
with everything there at min L and increase it later as needed to reach the
offset level you want.

At that point you'll know the best gm and input offset you could achieve at that
current level in the technology you are on.

I'll comment on the other stages later, I've got to go now.