Jan 28, 2013 #1 V Vishald Newbie level 1 Joined Oct 9, 2012 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,285 Actually I wanted to model a comparator for a pipelined 1.5 bit stage ADC considering all effects such as delay, rise time , fall time, input referred offset and resolution. How should I start?
Actually I wanted to model a comparator for a pipelined 1.5 bit stage ADC considering all effects such as delay, rise time , fall time, input referred offset and resolution. How should I start?