Comparator input bias current

[cupoftea]

Hi ,

We are doing the attached comparator circuit.
(LTspice and PNG schem as attached)
We must use one of the comparators in the STM32L073 micro (LQFP48).

STM32L073 Micro
https://www.st.com/en/microcontrollers-microprocessors/stm32l073cb.html

Page 115-116 of the STM32L073 datasheet does not provide figures for the small input
bias current at the inputs of its comparators. We need the 1MEG divider resistors as shown.
But we cant calculate the voltage that will be dropped across them by the input
bias current because the datasheet doesnt provide it.
Please advise if you can on the input bias current?

 

[FvM]

You are looking in the wrong place. Page 101 I/O port characteristics, +/- 50 nA maximal leakage current.

 

[cupoftea]

Thanks, though i see Pg 101 refers to the I/O's but isnt specifically referring to the comparator inputs?

 

[crutschow]

Thanks, though i see Pg 101 refers to the I/O's but isnt specifically referring to the comparator inputs?

It says all inputs except for the exceptions specified.

 

[cupoftea]

Thanks, but an I/O is the normal port gate input. A comparator input is classed as an analog input. Not the same.

 

[KlausST]

Hi,

I see your worries.
But we all reference to the same source of information: the datasheet.
And I see the same as FvM and crutschow.

So if you
* believe in the datasheet, then use the +/- 50nA.
* don´t believe in the datasheet: we can´t help you. You need to contact the manufacturer.

Klaus

 

[std_match]

To minimize the effect from the bias currents, both inputs should see the same DC resistance. Now one input sees 500k and the other 990k.
If you have them equal, only the delta bias current will matter, and it is probably very low.

 

[cupoftea]

Thanks,
So , may you please confirm that the attached gives a way of assessing the effects of the input bias
current in the comparator inside the STM32L073?

(LTspice and PNG schem as attached)

Obviously the worst case would be if the reference voltage goes "outside" the signal because then
we don't get an oscillating output as we should.

don´t believe in the datasheet: we can´t help you. You need to contact the manufacturer.

..Thankyou , i have done so as follows...but to no avail...

Also, I asked ST on their forum about the +/-magnitude of the input bias current to the internal comparators in the STM32L073,
and they would not answer there..
..they said they would contact me directly about it, but they have not done so.
As such, I believe that the information regarding this input bias current cannot be in the STM32L073 datasheet,
because if it was there, then they would have said so.

So in fact, the actual magnitude of the input bias current is still an open issue, and the correctness of the shown circuit
is completely up in the air.

I have no idea, but i suspect that a comparator thats on board a microcontroller is a cheap tatty thing with loads of input bias current?
I mean, surely if someone wants a low input bias current comparator then they add it externally?

 

[cupoftea]

Hi,,
Do you know if this comparator input bias current is more likely to be coming into the comparator's input pin or out of it?

 

[dick_freebird]

A CMOS comparator has no designed bias current, only ESD protection diodes leakage-balance (w/ VICM).

 

[cupoftea]

Thanks, so do you suppose that the comparartor's in the STM32L073 are CMOS and have no bias current?
Do you know why st.com refused to answer on this (on their forum)?.....if bias current was zero then surely they would have answered?
The fact they told me they wouldnt answer on their forum tells me the bias current must be high?

--- Updated Monday at 9:10 PM ---

A CMOS comparator has no designed bias current, only ESD protection diodes leakage-balance (w/ VICM).

Thanks, so normally when signal within rails no current from this?

--- Updated Monday at 10:43 PM ---

Hi,
The attached comparator circuit takes in some pulsing and turns it into a rail to rail pulsing.
(LTspice and PNG attached)
However, when no pulses come, the signals at the input to the comparator are just 100mV apart.
Also, it is the comparator inside the STM32L073 microcontroller, which has unspecified input bias current,
which may be higher than the 50nA shown here.
Also, the input divider resistances are MegOhm+ and could vary with moisture/dirt ingress.
Would you say this is a reliable design.?
Academically speaking it works, but its shoddy and has no need to be like this.
The circuitry could be easily changed to make the pulsing be rail to rail to the comparator input for example.

Would you go forward with this?....specially since input bias current of the comparator is unknown and may be
significantly higher than the 50nA shown and result in those inputs being even closer in voltage when no pulsing?

 

[dick_freebird]

What I see is a "1.8/3.3V CMOS" chip. No mention
of bipolars (which are the only devices that draw
significant input bias current; I've tested JFET-input
op amps out to 300C and they were still nanoamps).

The glass gate of a MOSFET draws nothing ('til you
break it). DC, anyhow.

There might be dynamic currents if the comparators
are autozero, clocked style. Those can be large but
ns-wide transients. The clock could charge-pump
a weak DC, high C input - or do so differentially,
again with the discrepant Zin. ST might disclose
stuff like that in app notes for analog interests.

I believe you want to assert a deadband and whether
100mV is reliable, goes to the end environment (plus
whatever baked-in noise is present). Such a thing does
not want to depend on an input bias current (highly
variable with processing, temperature, various abuses).
I'd look to develop the bias through reliable resistor
networks, then test against some sandbagged Iib
(per pin, could vary) and Vio limits.

 

[KlausST]

that the comparartor's in the STM32L073 are CMOS and have no bias current?

Dick_freebird used the phrase "designed" bias current.
I personally find this a quite suitable expression.

when you have a look at a BJT input stage of a comparator you usually have a transistor pair supplied with a (constant) emitter current.
This emitter current divided by the DC gain of the BJT is the base current of the BJT. THIS is the known (thus: designed) bias current.
It is quite well calculable.

On the other hand CMOS uses FETs instead of BJTs. FETs don´t have a calculable SOURCE dependent GATE current.
The GATE just suffers from leakage current. Not easy to calculate.

Klaus

 

[crutschow]

Any input leakage of a CMOS circuit input is due to the input protection diodes to ground and V+.
In this case it is specified as 50nA max, and is not designed or controlled, it's a function of the diodes construction and doping.
That should apply to all inputs, unless otherwise specified.

So you design the input impedances so that 50nA current does not exceed your accuracy requirements.